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cool solutions for wireless connectivity xemics sa ? e-mail: info@xemics.com ? web: www.xemics.com datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver XE88LC02 sensing machine data acquisition mcu with 16 + 10 bit zoomingadc and lcd driver general description the XE88LC02 is a data acquisition ultra low- power low-voltage microcontroller unit (mcu) with extremely high efficiency, allowing for 1 mips at 300ua and 2.4 v, and 8 x 8 bits multiplying in one clock cycle at 1.2 v. XE88LC02 includes a high resolution acquisition path with the 16+10 bits zoomingadc and an lcd driver for up to 1 20 segments. the lcd lines can be used as additional ios. XE88LC02 is available with on chip rom or multi- ple-time-programmable (mtp) program memory. applications ? portable, battery operated instruments ? rf system supervisor ? remote control ? hvac control ? metering ? sports watches, wrist instruments key product features ? low-power, high resolution zoomingadc ? 0.5 to 1000 gain with offset cancellation ? up to 16 bits adc ? up to 13 input multiplexer ? 4 low power comparators ? low-voltage low-powe r controller operation ? 2 mips with 2.4 v to 5.5 v operation ? 300 a at 1 mips over voltage range ? up to 7 mips in rom ? 1.2 v operation in rom ? 22 kbyte (8 kinstruction) mtp ? 1032 byte ram data memory ? rc and crystal oscillators ? 5 reset, 22 interrupt, 8 event sources ? 120 segments lcd driver ? can be used as extra io ? 100 years mtp flash retention at 55c ordering information product temperature range memory type package XE88LC02mi000 -40c to 85 c mtp die XE88LC02mi035 -40c to 85 c mtp lqfp100
d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table of contents chapter 1 XE88LC02 overview chapter 2 XE88LC02 performance chapter 3 XE88LC02 cpu chapter 4 XE88LC02 memory chapter 5 low power modes chapter 6 reset generator chapter 7 clock generation chapter 8 interrupt handler chapter 9 event handler chapter 10 low power ram chapter 11 port a chapter 12 port b chapter 13 port d chapter 14 universal asynchronous receiver/transmitter (uart) chapter 15 universal synchronous receiver/transmitter (usrt) chapter 16 serial peripheral interface (spi) chapter 17 acquisition chain chapter 18 voltage multiplier chapter 19 lcd driver chapter 20 counters/pwm chapter 21 the voltage level detector chapter 22 low power comparators chapter 23 XE88LC02 dimensions
1-1 lc02 - 1.1 ? 04 november 2002 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 1. general overview 1.1 top schematic 1-2 1.2 pin map 1-4 1.2.1 lqfp-100 1-4 1.2.2 lqfp-80 1-6 1.3 pin assignment 1-7
1-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 1.1 top schematic the top-level block schematic of the circuit is shown in figure 1-1. the heart of the circuit consists of the coolrisc816 cpu core. this core includes an 8x8 multiplier and 16 internal registers. the bus controller generates all control signals for access to all data registers other than the cpu internal registers. the reset block generates the adequate reset signals for t he rest of the circuit as a function of the set- up contained in its control registers. possible re set sources are the power-on-reset (por), the external pin nreset, the watchdog (wd), a bus error detected by the bus controller or a programmable pattern on port a. differ ent low power modes are implemented. the clock generation and power management block se ts up the clock signals and generates internal supplies for different blocks. the clock can be gener ated from the rc oscillator (this is the start-up condition), the crystal oscillator (xtal) or an ex ternal clock source (given on the xin pin). the test controller generates all set-up signals for diffe rent test modes. in normal operation, it is used as a set of 8 low power data registers. if power consumption is important for the application, the variables that need to be accessed frequently should be stored in these registers rather than in the ram. the irq handler routes the interrupt signals of the different peripherals to t he irq inputs of the cpu core. it allows masking of the interrupt sources and it flags which interrupt source is active. events are generally used to restart the processor a fter a halt period without jumping to a specified address, i.e. the program executi on resumes with the instruction fo llowing the halt instruction. the evn handler routes the event signals of the different peripherals to t he evn inputs of the cpu core. it allows masking of the interrupt sources and it flags which interrupt source is active. the port b is an 8 bit parallel io port with analog capabilities. the urst, uart, pwm and cmpd block also make use of this port. the instruction memory is a 22-bit wide flash or rom memory depending on the circuit version. in case of the rom version, the vpp pin is not used. flash and rom versions have both 8k instruction memory. the data memory on this product is a 1024 byte sram. the acquisition chain is a high-resolution ac quisition path with the 16+10 bits zoomingadc ? . the vmult (voltage multiplier) powers a part of the acquisition chain. the spi is a serial interface with a master or slave configuration capabilit y. when unused, the 4 spi pads can be used as 4-bit wide general-purpose i/o port. the port a is an 8 bit parallel input port. it can al so generate interrupts, events or a reset. it can be used to input external clocks fo r the timer/counter/pwm block. the port d1 and the port d2 are two general-purpose 8 bit parallel i/o ports. the lcd driver can support a direct drive display (up to 32 segments), or multiplex 1/2, 1/3, 1/4 displays (up to 120 segments). the driver cont ains an on chip low-power voltage generation device vgen. the lcd lines can be used as additional i/o pins. the usrt (universal synchronous receiver/transmitte r) contains some simple hardware functions in order to simplify the software implement ation of a synchronous serial link.
1-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver instruction memory b u s c o n t r o l l e r test controller reset block wd clock generation/ power management vreg xtal rc cpu coolrisc816 8 x 8 multiplier 16 cpu registers irq handling evn handling port b 8 data registers port a usrt port d1 address control datain dataout reset control clocks test control irq evn vpp vbat vss nreset xin xout vreg test pb(7:0) vmult ac_r(3:0) ac_a(7:0) spi(3:0) pa(7:0) pd1(7:0) pd2(7:0) lcd_io(31:0) lcd_com(1:0) vgen_vx(4:0) data memory uart counters timers pwm vld cmpd pb(5:4) pb(7:6) pa(3:0) pb(1:0) pb(7:4) por port d2 acquisition chain vmult (zoomingadc) lcd driver vgen spi figure 1-1. block schematic of the XE88LC02 circuit.
1-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the uart (universal asynchronous receiver/transmi tter) contains a full hardware implementation of the asynchronous serial link. the counters/timers/pwm can take its clocks from in ternal or external sources (on port a) and can generate interrupts or events. t he pwm is output on port b. the vld (voltage level detector) detects the batte ry end of life with respect to a programmable threshold. the cmpd contains a 4-channel comparator. it is intended to monitor analog or digital signals with very low power consumption. 1.2 pin map the lc02 can be delivered in different packages. the pin maps for the different packages are given below. 1.2.1 lqfp-100 20 10 1 vmult vreg vbat xout vss xin ac_r(2) ac_r(3) ac_r(0) ac_r(1) ac_a(7) ac_a(6) ac_a(5) ac_a(4) ac_a(3) ac_a(2) ac_a(1) ac_a(0) test n reset pd2(7) pd2(6) pd2(5) pd2(4) pd2(3) lcd_vr2 lcd_io(0) lcd_io(1) lcd_io(2) lcd_io(3) lcd_vr1 lcd_io(4) lcd_io(5) lcd_io(6) lcd_io(7) lcd_io(8) lcd_io(9) lcd_io(10) lcd_io(11) lcd_io(12) lcd_io(13) lcd_io(14) lcd_io(15) lcd_io(16) lcd_io(17) lcd_io(18) lcd_io(19) lcd_io(20) lcd_io(21) lcd_io(22) lcd_io(23) lcd_io(24) lcd_io(25) lcd_io(26) lcd_io(27) lcd_io(28) lcd_io(29) lcd_io(30) lcd_io(31) lcd_com(1) lcd_com(0) vgen_va vgen_v1 vgen_v2 vgen_v3 vgen_vb vss vbat pd1(0) pa(0) pd1(1) pa(1) pd2(0) pd2(1) pd2(2) vpp spi(3) spi(2) spi(1) spi(0) pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) pd1(7) pa(7) pd1(6) pa(6) pd1(5) pa(5) pd1(4) pa(4) pd1(3) pa(3) pd1(2) pa(2) 60 70 50 40 30 80 90 figure 1-2. lqfp-100 pin map
1-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver package pin name package pin name 1 pd2(3) 51 lcd_vr2 2 pd2(4) 52 lcd_io(0) 3 pd2(5) 53 lcd_io(1) 4 pd2(6) 54 lcd_io(2) 5 pd2(7) 55 lcd_io(3) 6 nreset 56 lcd_vr1 7 test 57 lcd_io(4) 8 ac_a(0) 58 lcd_io(5) 9 ac_a(1) 59 lcd_io(6) 10 ac_a(2) 60 lcd_io(7) 11 ac_a(3) 61 lcd_io(8) 12 ac_a(4) 62 lcd_io(9) 13 ac_a(5) 63 lcd_io(10) 14 ac_a(6) 64 lcd_io(11) 15 ac_a(7) 65 lcd_io(12) 16 ac_r(1) 66 lcd_io(13) 17 ac_r(0) 67 lcd_io(14) 18 ac_r(3) 68 lcd_io(15) 19 ac_r(2) 69 lcd_io(16) 20 xin 70 lcd_io(17) 21 vss 71 lcd_io(18) 22 xout 72 lcd_io(19) 23 vbat 73 lcd_io(20) 24 vreg 74 lcd_io(21) 25 vmult 75 lcd_io(22) 26 pa(2) 76 lcd_io(23) 27 pd1(2) 77 lcd_io(24) 28 pa(3) 78 lcd_io(25) 29 pd1(3) 79 lcd_io(26) 30 pa(4) 80 lcd_io(27) 31 pd1(4) 81 lcd_io(28) 32 pa(5) 82 lcd_io(29) 33 pd1(5) 83 lcd_io(30) 34 pa(6) 84 lcd_io(31) 35 pd1(6) 85 lcd_com(1) 36 pa(7) 86 lcd_com(0) 37 pd1(7) 87 vgen_va 38 pb(0) 88 vgen_v1 39 pb(1) 89 vgen_v2 40 pb(2) 90 vgen_v3 41 pb(3) 91 vgen_vb 42 pb(4) 92 vss 43 pb(5) 93 vbat 44 pb(6) 94 pd1(0) 45 pb(7) 95 pa(0) 46 spi(0) 96 pd1(1) 47 spi(1) 97 pa(1) 48 spi(2) 98 pd2(0) 49 spi(3) 99 pd2(1) 50 vpp 100 pd2(2) table 1-1. bonding plan of the lqfp- 100 package (lqfp 100l 14x14mm thick 1.6 mm)
1-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 1.2.2 lqfp-80 package pin name package pin name 1 nreset 41 lcd_vr1 2 test 42 lcd_io(4) 3 ac_a(0) 43 lcd_io(5) 4 ac_a(1) 44 lcd_io(6) 5 ac_a(2) 45 lcd_io(7) 6 ac_a(3) 46 lcd_io(8) 7 ac_a(4) 47 lcd_io(9) 8 ac_a(5) 48 lcd_io(10) 9 ac_a(6) 49 lcd_io(11) 10 ac_a(7) 50 lcd_io(12) 11 ac_r(1) 51 lcd_io(13) 12 ac_r(0) 52 lcd_io(14) 13 ac_r(3) 53 lcd_io(15) 14 ac_r(2) 54 lcd_io(16) 15 xin 55 lcd_io(17) 16 vss 56 lcd_io(18) 17 xout 57 lcd_io(19) 18 vbat 58 lcd_io(20) 19 vreg 59 lcd_io(21) 20 vmult 60 lcd_io(22) 21 pa(2)/ pd1(2) 61 lcd_io(23) 22 pa(3)/ pd1(3) 62 lcd_io(24) 23 pa(4)/ pd1(4) 63 lcd_io(25) 24 pa(5)/ pd1(5) 64 lcd_io(26) 25 pa(6)/ pd1(6) 65 lcd_io(27) 26 pa(7) 66 lcd_io(28) 27 pd1(7) 67 lcd_io(29) 28 pb(0) 68 lcd_io(30) 29 pb(1) 69 lcd_io(31) 30 pb(2) 70 lcd_com(1) 31 pb(3) 71 lcd_com(0) 32 pb(4) 72 vgen_va 33 pb(5) 73 vgen_v1 34 pb(6) 74 vgen_v2 35 pb(7) 75 vgen_v3 36 spi(0) 76 vgen_vb 37 spi(1) 77 vss 38 spi(2) 78 vbat 39 spi(3) 79 pa(0)/pd1(0) 40 vpp 80 pa(1)/ pd1(1) table 1-2. bonding plan of the lqfp- 80 package (lqfp 80l 14x14mm thick 1.6 mm)
1-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 70 80 20 10 1 vmult vreg vbat xout vss xin ac_r(2) ac_r(3) ac_r(0) ac_r(1) ac_a(7) ac_a(6) ac_a(5) ac_a(4) ac_a(3) ac_a(2) ac_a(1) ac_a(0) test n reset lcd_vr1 lcd_io(4) lcd_io(5) lcd_io(6) lcd_io(7) lcd_io(8) lcd_io(9) lcd_io(10) lcd_io(11) lcd_io(12) lcd_io(13) lcd_io(14) lcd_io(15) lcd_io(16) lcd_io(17) lcd_io(18) lcd_io(19) lcd_io(20) lcd_io(21) lcd_io(22) lcd_io(23) lcd_io(24) lcd_io(25) lcd_io(26) lcd_io(27) lcd_io(28) lcd_io(29) lcd_io(30) lcd_io(31) lcd_com(1) lcd_com(0) vgen_va vgen_v1 vgen_v2 vgen_v3 vgen_vb vss vbat pd1(0)/pa(0) pd1(1)/pa(1) vpp spi(3) spi(2) spi(1) spi(0) pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) pd1(7) pa(7) pd1(6)/pa(6) pd1(5)/pa(5) pd1(4)/pa(4) pd1(3)/pa(3) pd1(2)/pa(2) 50 60 40 30 figure 1-3. lqfp- 80 pin map 1.3 pin assignment the table below gives a short descripti on of the different pin assignments. pin assignment vbat positive power supply vss negative power supply vreg connection for the mandatory external capacitor of t he voltage regulator vpp high voltage supply for flash memory programming (nc in rom versions) nreset resets the circuit when the voltage is low test sets the pin to flash programming mode xin/xout quartz crystal connections, al so used for flash memory programming pa(7:0) parallel input port a pins pb(7:0) parallel i/o port b pins pd1(7:0) parallel i/o port d1 pins pd2(7:0) parallel i/o port d2 pins spi(3:0) serial spi port or general purpose i/o port pins lcd_io(29:0) lcd segment driver or general purpose i/o port pins lcd_io(31:30) lcd segment driver or lcd ba ck plane driver or general purpose i/o port pins lcd_com(1:0) lcd back plane driver pins lcd_vr1/lcd_vr2 lcd supply voltage vgen_vx lcd driver voltage generation pins ac_a(7:0) acquisition chain input pins ac_r(3:0) acquisition chain reference pins vmult connection for external capac itor of the voltage multiplier table 1-3. pin assignment
1-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table 1-4 gives a more detailed pin map for the di fferent pins in the different packages. it also indicates the possible i/o configuration of t hese pins. the indications in blue bold are the configuration at start-up. please note that in the lqfp-80 package se veral functions are routed to the same package pins. these pins are indicated in red italic. pin number function i/o configuration lqfp-100 lqfp-80 first second third ai ao di do od pu pd snap lcd power 1 pd2(3) x x x x 2 pd2(4) x x x x 3 pd2(5) x x x x 4 pd2(6) x x x x 5 pd2(7) x x x x 6 1 nreset x x 7 2 test x x 8 3 ac_a(0) x 9 4 ac_a(1) x 10 5 ac_a(2) x 11 6 ac_a(3) x 12 7 ac_a(4) x 13 8 ac_a(5) x 14 9 ac_a(6) x 15 10 ac_a(7) x 16 11 ac_r(1) x 17 12 ac_r(0) x 18 13 ac_r(3) x 19 14 ac_r(2) x 20 15 xin x x 21 16 vss x 22 17 xout x x 23 18 vbat x 24 19 vreg x 25 20 vmult x 26 21 pa(2) cntc x x x 27 21 pd1(2) x x x x 28 22 pa(3) cntd x x x 29 22 pd1(3) x x x x 30 23 pa(4) x x x 31 23 pd1(4) x x x x 32 24 pa(5) x x x 33 24 pd1(5) x x x x 34 25 pa(6) x x x 35 25 pd1(6) x x x x 36 26 pa(7) x x x 37 27 pd1(7) x x x x 38 28 pb(0) pwm0 x x x xx x 39 29 pb(1) pwm1 x x x xx x 40 30 pb(2) x x x xx x 41 31 pb(3) x x x xx x 42 32 pb(4) usrt_s0 cmpd(0) x x x xx x
1-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 43 33 pb(5) usrt_s1 cmpd(1) x x x xx x 44 34 pb(6) uart_tx cmpd(2) x x x xx x 45 35 pb(7) uart_rx cmpd(3) x x x xx x 46 36 spi(0) x x x 47 37 spi(1) x x x 48 38 spi(2) x x x 49 39 spi(3) x x x 50 40 vpp x 51 lcd_vr2 x 52 lcd_io(0) xx x x 53 lcd_io(1) xx x x 54 lcd_io(2) xx x x 55 lcd_io(3) xx x x 56 41 lcd_vr1 x 57 42 lcd_io(4) xx x x 58 43 lcd_io(5) xx x x 59 44 lcd_io(6) xx x x 60 45 lcd_io(7) xx x x 61 46 lcd_io(8) xx x x 62 47 lcd_io(9) xx x x 63 48 lcd_io(10) xx x x 64 49 lcd_io(11) xx x x 65 50 lcd_io(12) xx x x 66 51 lcd_io(13) xx x x 67 52 lcd_io(14) xx x x 68 53 lcd_io(15) xx x x 69 54 lcd_io(16) xx x x 70 55 lcd_io(17) xx x x 71 56 lcd_io(18) xx x x 72 57 lcd_io(19) xx x x 73 58 lcd_io(20) xx x x 74 59 lcd_io(21) xx x x 75 60 lcd_io(22) xx x x 76 61 lcd_io(23) xx x x 77 62 lcd_io(24) xx x x 78 63 lcd_io(25) xx x x 79 64 lcd_io(26) xx x x 80 65 lcd_io(27) xx x x 81 66 lcd_io(28) xx x x 82 67 lcd_io(29) xx x x 83 68 lcd_io(30) xx x x 84 69 lcd_io(31) xx x x 85 70 lcd_com(1) x 86 71 lcd_com(0) x 87 72 vgen_va x 88 73 vgen_v1 x x 89 74 vgen_v2 x x 90 75 vgen_v3 x x
1-10 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 91 76 vgen_vb x 92 77 vss x 93 78 vbat x 94 79 pd1(0) x x x x 95 79 pa(0) cnta x x x 96 80 pd1(1) x x x x 97 80 pa(1) cntb x x x 98 pd2(0) x x x x 99 pd2(1) x x x x 100 pd2(2) x x x x pin map table legend: blue bold: configuration at start up ai: analog input ao: analog output di: digital input do: digital output od: nmos open drain output pu: pull-up resistor pd: pull-down resistor snap: snap-to-rail function (see peripheral description for detailed description) power: power supply table 1-4. pin description table
2-1 lc02 - 1.1 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2 XE88LC02 performance 2.1 absolute maximum ratings 2-2 2.2 operating range 2-2 2.3 current consumption 2-3 2.4 operating speed 2-5 2.4.1 flash circuit version 2-5 2.4.2 rom circuit version with regulator on 2-6 2.4.3 rom circuit version with regulator off 2-7 2.5 simplified supply selection criteria 2-8
2-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2.1 absolute maximum ratings table 2-1. absolute maximal ratings min. max. note voltage applied to vbat with respect to vss -0.3 6.0 v voltage applied to vpp with respect to vss vbat-0.3 12 v voltage applied to all pins except vpp and vbat vss-0.3 vbat+0.3 v storage temperature (rom device or unprogrammed flash device) -55 150 c storage temperature (programmed flash device) -40 85 c stresses beyond the absolute maximal ratings may cause permanent damage to the device. functional operation at the absolute maximal ratings is not implied. exposure to conditions beyond the absolute maximal ratings may affe ct the reliability of the device. 2.2 operating range table 2-2. operating range for the flash device min. max. note voltage applied to vbat with respect to vss 2.4 5.5 v voltage applied to vbat with respect to vss during the flash programming 4.5 5.5 v 1 voltage applied to vpp with respect to vss vbat 11.5 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 85 c capacitor on vreg (flash version) 0.8 1.2 f 2 capacitor on vmult 1.0 3.0 nf 3 1. during the programming of the device t he temperature must be between 10c and 40c. 2. the capacitor on vreg is mandatory. 3. the capacitor on vmult is optional. the capac itor has to be present if the multiplier is enabled. the multiplier has to be enabled if vbat<3.0v. table 2-3. operating range for the rom device min. max. note vreg by- passed 1.2 5.5 v 2 acquisition chain off vreg on 1.5 5.5 v vmult on 2.4 5.5 v voltage applied to vbat with respect to vss acquisition chain on vmult off 3.0 5.5 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 125 c capacitor on vreg 0.1 1.2 f 1 capacitor on vmult 1.0 3.0 nf 3 1. the capacitor may be omitt ed when vreg is connected to vbat. 2. the voltage reference for the lcd drivers starts operating at 1.5 v. 3. the capacitor on vmult is optional. the capac itor has to be present if the multiplier is enabled. the multiplier has to be enabled if vbat<3.0v.
2-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver all specifications in this document are valid for the complete operating range unless otherwise specified. table 2-4. operating range of the flash memory min. max. note retention time at 85c 10 years 1 retention time at 55c 100 years 1 number of programming cycles 10 2 1. valid only if programmed using a programming tool that is qualified 2. circuits can be programmed more than 10 times but in that case, the retention time is no longer guaranteed. 2.3 current consumption the tables below give the current consumption for t he circuit in different configurations. the figures are indicative only and may change as a function of the actual software implemented in the circuit. table 2-5 gives the current consumption for the flash version of the circuit. the peripherals are disabled. the parallel ports are configured in i nput with pull up. their pins are not connected externally. table 2-5. typical current consumption of the XE88LC02m version (8k instructions flash memory) operation mode cpu rc xtal consumption comments note high speed cpu 1 mips 1 mhz off 200 a 2.4v<>5.5v, 27 c 1 320 a 2 410 a 3 310 a 4 low speed cpu .1 mips 100 khz off 21 a 2.4v <>5.5v, 27 c 1 33 a 2 42 a 3 low power cpu 32 kips off 32 khz 7.5 a 2.4v <>5.5v, 27 c 1 11.0 a 2 14.5 a 3 low power time keeping halt off 32 khz 1.9 a 2.4v <>5.5v, 27 c fast wake-up time keeping halt ready 32khz 2.3 a 2.4v <>5.5v, 27 c immediate wake- up time keeping halt 1 mhz off 35 a 2.4v <>5.5v, 27 c vld static current 15 a 2.4v <>5.5v, 27 c cmpd static current 2 a 2.4v <>5.5v, 27 c 1. software without data access 2. 100% low power ram access 3. 100% ram access 4. typical software
2-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table 2-6. current consumption of the xe88lc 02r version (8k instructions rom memory) operation mode cpu rc xtal consumption comments note high speed cpu 1 mips 1 mhz off 200 2.4v<>5.5v, 27 c 1 max. speed cpu 4 mips 4 mhz off 800 2.4v<>5.5v, 27 c 1 low speed cpu .1 mips 100 khz off 21 2.4v <>5.5v, 27 c 1 low power cpu 32 kips off 32 khz 7 2.4v <>5.5v, 27 c 1 low voltage cpu 32 kips off 32 khz 1 1.2v, 27 c 1 low power time keeping halt off 32 khz 1.3 2.4v <>5.5v, 27 c 1. software using move instruction using in ternal cpu registers and peripheral registers hints for low power operation: 1. use the low power ram instead of the ram fo r all parameters that are accessed frequently. the average current consumption for the low power ram is about 40 times lower than for the ram. 2. rather than using the circuit at low speed, it is better to use the circuit at higher speed and switch off the blocks when not needed. 3. the power consumption of the program memo ry is an important part of the overall power consumption. in case you intend to use a ro m version and power consumption is too high, please ask us to provide you with a circuit version with smaller rom size.
2-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2.4 operating speed 2.4.1 flash circuit version the speed of the flash devices is not highly dependent upon the supply voltage. however, by limiting the temperature range, the speed can be increased. the minimal guaranteed speed as a function of the supply voltage and maximal temperature operat ing temperature is given in figure 2-1. vbat vreg vss 2.4 - 5.5 v 1uf figure 2-2. supply configurati on for flash circuit operation. 0 0.5 1 1.5 2 2.5 3 3.5 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c figure 2-3. guaranteed speed as a function of the supply voltage and maximal temperature. note that the speed of the flash circuit version is limited by the flash memory . all other peripherals of the device can run at the same speed as the ro m version (see figure 2-5). the maximal speed of the peripherals can be exploited by reducing the cpu frequency by a factor of 2 with respect to the clock source by executing the inst ruction ?freq div2?. take care to execute this instruction before increasing the clock speed above the figures given in figure 2-3.
2-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2.4.2 rom circuit version with regulator on for the rom version, two possible operating modes exist: with and without voltage regulator. using the voltage regulator, low power consumption w ill be obtained even with supply voltages above 2.4v. without the voltage regulator (i.e. vreg short-ci rcuited to vbat), a higher speed can be obtained. vbat vreg vss 2.4 - 5.5 v 100nf figure 2-4. supply configuration for rom circ uit operation using the internal regulator. 0 2 4 6 8 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-5. guaranteed speed as a function of suppl y voltage and for different maximal temperatures using the voltage regulator.
2-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2.4.3 rom circuit version with regulator off vbat vreg vss 1.2 ? 3.3 v figure 2-6. supply configuration for rom circui t operation by-passing the internal regulator. 0 2 4 6 8 11.522.533.5 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-7. guaranteed speed as a function of s upply voltage and for two temperature ranges when vreg=vbat. important note note that the acquisition chain will not operate if vbat is below 2.4v. the internal reference voltage for the lcd will not operate below 1.5v. if the in ternal reference is not used, the lcd voltage generator and the lcd driver will operate down to 1.2v . the operation range of the different blocks is summarized in figure 2-8.
2-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 2.5 simplified supply selection criteria ? mtp devices always require the capacitor on vreg and vreg cannot be shorted to vbat on mtp devices. ? rom devices can operate 1.5 v to 5.5 v with lo west current requirement with the capacitor on vreg, and vreg not shorted to vbat. ? rom devices can operate 1.2 v to 3.3 v at highest speed with vreg shorted to vbat. ? if operation is always above 3.0 v, the c apacitor on vmult is not needed and vmult can be always off. ? if the acquisition chain is used between 2.4 v and 3.0 v, then the capacitor on vmult must be present and vmult must be set on during operation below 3.0 v. ? the acquisition chain does not operate below 2.4 v. ? the internal reference voltage for the lcd does not operate below 1.5 v. 0 1.2 1.5 2.4 3.0 5.5 vbat (v) cpu parallel and serial ports lcd driver and vgen (no int. ref.) rc and crystal oscillator vld comparators counters and pwm vgen internal reference acquisition chain vmult on acquisition chain vmult off rom (vbat=vreg) rom (vbat vreg) mtp figure 2-8. operating voltage range of the different circuit blocks. mtp devices do not operate below 2.4v. rom devices can operate in different voltage ranges if vreg and vbat are short circuited or not.
3-1 d0309-136 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 3. cpu 3.1 cpu description 3-2 3.2 cpu internal registers 3-2 3.3 cpu instruction short reference 3-4
3-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 3.1 cpu description the cpu of the xe8000 series is a low power risc core. it has 16 internal registers for efficient implementation of the c compiler. its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. all instructi ons are executed in one clock cycle, including conditional jumps and 8x8 multiplication. the circui t therefore runs on 1 mips on a 1mhz clock. the cpu hardware and software description is gi ven in the document ?coolrisc816 hardware and software reference manual?. a short summa ry is given in the following paragraphs. the good code efficiency of the cpu core make s it possible to compute a polynomial like y b b x y a a z ? + + ? ? + = 1 0 1 0 ) ( in less than 300 clock cycles (software code generated by the xemics c-compiler, all numbers are signed integers on 16 bits). 3.2 cpu internal registers as shown in figure 3-1, the cpu has 16 internal 8-bit registers. some of these registers can be concatenated to a 16-bit word for use in some instru ctions. the function of t hese registers is defined in table 3-1. the status register stat (table 3-2) is used to m anage the different interrupt and event levels. an interrupt or an event can both be used to wake up after a halt instruction. the difference is that an interrupt jumps to a special interrupt function whereas an event continues the software execution with the instruction fo llowing the halt instruction. the program counter (pc) is a 16 bit register that indicates the address of the instruction that has to be executed. the stack (st n ) is used to memorise the return address when executing subroutines or interrupt routines. instruction memory 22bit cpu cpu internal registers a stat iph ipl i3h i3l i2h i2l i1h i1l i0h i0l r3 r2 r1 r0 data memory data bus instruction bus pc st 1 st 2 st 3 st 4 program counter stack figure 3-1. cpu internal registers
3-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver register name register function r0 general purpose r1 general purpose r2 general purpose r3 data memory offset i0h msb of the data memory index i0 i0l lbs of the data memory index i0 i1h msb of the data memory index i1 i1l lbs of the data memory index i1 i2h msb of the data memory index i2 i2l lbs of the data memory index i2 i3h msb of the data memory index i3 i3l lbs of the data memory index i3 iph msb of the program memory index ip ipl lbs of the program memory index ip stat status register a accumulator table 3-1. cpu internal register definition bit name function 7 ie2 enables (when 1) the interrupt request of level 2 6 ie1 enables (when 1) the interrupt request of level 1 5 gie enables (when 1) all interrupt request levels 4 in2 interrupt request of level 2. the interr upts labelled ?low? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 3 in1 interrupt request of level 1. the interr upts labelled ?mid? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 2 in0 interrupt request of level 0. the interr upts labelled ?hig? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 1 ev1 event request of level 1. the events labe lled ?low? in the event handler are routed to this event level. this bit has to be cleared when the event is served. 0 ev0 event request of level 1. the events labe lled ?hig? in the event handler are routed to this event level. this bit has to be cleared when the event is served. table 3-2. status register description the cpu also has a number of flags that can be used for conditional jumps. these flags are defined in table 3-3. symbol name function z zero z=1 when the accumulator a content is zero c carry this flag is used in sh ift or arithmetic operations. for a shift operation, it has the value of the bit that was shifted out (lsb for shift right, msb for shift left). for an arithmetic operation with unsigned numbers: it is 1 at occurrence of an overfl ow during an addition (or equivalent). it is 0 at occurrence of an underflow during a subtraction (or equivalent). v overflow this flag is used in shift or arithmetic operations. for arithmetic or shift operations with signed numbers, it is 1 if an overflow or underflow occurs. table 3-3. flag description
3-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 3.3 cpu instruction short reference table 3-4 shows a short description of the different instructions availabl e on the coolrisc816. the notation cc in the conditional jump instruction refers to the condition description as given in table 3-6. the notation reg, reg1, reg2, reg3 refers to one of the cpu inter nal registers of table 3-1. the notation eaddr and dm(eaddr) refer to one of the extended address modes as defined in table 3-5. the notation dm(xxx) refers to the data memory location with address xxx. instruction modification operation jump addr[15:0] -,-,-, - pc := addr[15:0] jump ip -,-,-, - pc := ip j cc addr[15:0] -,-,-, - if cc is true then pc := addr[15:0] j cc ip -,-,-, - if cc is true then pc := ip call addr[15:0] -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := addr[15:0] call ip -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := ip calls addr[15:0] -,-,-, - ip := pc+1; pc := addr[15:0] calls ip -,-,-, - ip := pc+1; pc := ip ret -,-,-, - pc := st 1 ; st n := st n+1 (n>1) rets -,-,-, - pc := ip reti -,-,-, - pc := st 1 ; st n := st n+1 (n>1); gie :=1 push -,-,-, - pc := pc+1; st n+1 := st n (n>1); st 1 := ip pop -,-,-, - pc := pc+1; ip := st 1 ; st n := st n+1 (n>1) move reg ,#data[7:0] -,-, z, a a := data[7:0]; reg := data[7:0] move reg1 , reg2 -,-, z, a a := reg2 ; reg1 := reg2 move reg , eaddr -,-, z, a a := dm(eaddr) ; reg := dm(eaddr) move eaddr , reg -,-,-, - dm(eaddr) := reg move addr[7:0],#data[7:0] -,-,-, - dm(addr[7:0]) := data[7:0] cmvd reg1 , reg2 -,-, z, a a := reg2 ; if c=0 then reg1 := a; cmvd reg , eaddr -,-, z, a a := dm(eaddr) ; if c=0 then reg := a cmvs reg1 , reg2 -,-, z, a a := reg2 ; if c=1 then reg1 := a; cmvs reg , eaddr -,-, z, a a := dm(eaddr) ; if c=1 then reg := a shl reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := 0; c := reg2[7] ; reg1 := a shl reg c, v, z, a a := reg <<1; a[0] := 0; c := reg[7] ; reg := a shl reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] ; reg := a shlc reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := c; c := reg2[7] ; reg1 := a shlc reg c, v, z, a a := reg <<1; a[0] := c; c := reg[7] ; reg := a shlc reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] := c; c := dm(eaddr)[7] ; reg := a shr reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := 0; c := reg2[0] ; reg1 :=a shr reg c, v, z, a a := reg >>1; a[7] := 0; c := reg[0] ; reg := a shr reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := 0; c := dm(eaddr)[0] ; reg := a shrc reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := c; c := reg2[0] ; reg1 := a shrc reg c, v, z, a a := reg >>1; a[7] := c; c := reg[0] ; reg := a shrc reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := c; c := dm(eaddr)[0] ; reg := a shra reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := reg2[7] ; c := reg2[0] ; reg1 := a shra reg c, v, z, a a := reg >>1; a[7] := reg[7] ; c := reg[0] ; reg := a shra reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := dm(eaddr)[7] ; c := dm(eaddr)[0] ; reg := a cpl1 reg1 , reg2 -,-, z, a a := not( reg2 ); reg1 := a cpl1 reg -,-, z, a a := not( reg ); reg := a cpl1 reg , eaddr -,-, z, a a := not( dm(eaddr) ); reg := a cpl2 reg1 , reg2 c, v, z, a a := not( reg2 )+1; if a=0 then c:=1 else c := 0; reg1 := a cpl2 reg c, v, z, a a := not( reg )+1; if a=0 then c:=1 else c := 0; reg := a cpl2 reg , eaddr c, v, z, a a := not( dm(eaddr) )+1; if a=0 then c:=1 else c := 0; reg := a cpl2c reg1 , reg2 c, v, z, a a := not( reg2 )+c; if a=0 and c=1 then c:=1 else c := 0; reg1 := a cpl2c reg c, v, z, a a := not( reg )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a cpl2c reg , eaddr c, v, z, a a := not( dm(eaddr) )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a inc reg1 , reg2 c, v, z, a a := reg2 +1; if a=0 then c := 1 else c := 0; reg1 := a inc reg c, v, z, a a := reg +1; if a=0 then c := 1 else c := 0; reg := a inc reg , eaddr c, v, z, a a := dm(eaadr) +1; if a=0 then c := 1 else c := 0; reg := a incc reg1 , reg2 c, v, z, a a := reg2 +c; if a=0 and c=1 then c := 1 else c := 0; reg1 := a incc reg c, v, z, a a := reg +c; if a=0 and c=1 then c := 1 else c := 0; reg := a incc reg , eaddr c, v, z, a a := dm(eaadr) +c; if a=0 and c=1 then c := 1 else c := 0; reg := a dec reg1 , reg2 c, v, z, a a := reg2 -1; if a=hff then c := 0 else c := 1; reg1 := a
3-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver dec reg c, v, z, a a := reg -1; if a=hff then c := 0 else c := 1; reg := a dec reg , eaddr c, v, z, a a := dm(eaddr) -1; if a=hff then c := 0 else c := 1; reg := a decc reg1 , reg2 c, v, z, a a := reg2 -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg1 := a decc reg c, v, z, a a := reg -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a decc reg , eaddr c, v, z, a a := dm(eaddr) -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a and reg ,#data[7:0] -,-, z, a a := reg and data[7:0]; reg := a and reg1 , reg2 , reg3 -,-, z, a a := reg2 and reg3 ; reg1 := a and reg1 , reg2 -,-, z, a a := reg1 and reg2 ; reg1 := a and reg , eaddr -,-, z, a a := reg and dm(eaddr) ; reg := a or reg ,#data[7:0] -,-, z, a a := reg or data[7:0]; reg := a or reg1 , reg2 , reg3 -,-, z, a a := reg2 or reg3 ; reg1 := a or reg1 , reg2 -,-, z, a a := reg1 or reg2 ; reg1 := a or reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a xor reg ,#data[7:0] -,-, z, a a := reg xor data[7:0]; reg := a xor reg1 , reg2 , reg3 -,-, z, a a := reg2 xor reg3 ; reg1 := a xor reg1 , reg2 -,-, z, a a := reg1 xor reg2 ; reg1 := a xor reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a add reg ,#data[7:0] c, v, z, a a := reg +data[7:0]; if overflow then c:=1 else c := 0; reg := a add reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 ; if overflow then c:=1 else c := 0; reg1 := a add reg1 , reg2 c, v, z, a a := reg1 + reg2 ; if overflow then c:=1 else c := 0; reg1 := a add reg , eaddr c, v, z, a a := reg + dm(eaddr) ; if overflow then c:=1 else c := 0; reg := a addc reg ,#data[7:0] c, v, z, a a := reg +data[7:0]+c; if overflow then c:=1 else c := 0; reg := a addc reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg1 , reg2 c, v, z, a a := reg1 + reg2 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg , eaddr c, v, z, a a := reg + dm(eaddr) +c; if overflow then c:=1 else c := 0; reg := a subd reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c := 0 else c := 1; reg := a subd reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 ; if underflow then c := 0 else c := 1; reg1 := a subd reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c := 0 else c := 1; reg1 := a subd reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c := 0 else c := 1; reg := a subdc reg ,#data[7:0] c, v, z, a a := data[7:0]- reg -(1-c); if underflow then c := 0 else c := 1; reg := a subdc reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg1 , reg2 c, v, z, a a := reg2 - reg1 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg , eaddr c, v, z, a a := dm(eaddr) - reg -(1-c); if underflow then c := 0 else c := 1; reg := a subs reg ,#data[7:0] c, v, z, a a := reg -data[7:0]; if underflow then c := 0 else c := 1; reg := a subs reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg1 , reg2 c, v, z, a a := reg1 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg , eaddr c, v, z, a a := reg - dm(eaddr) ; if underflow then c := 0 else c := 1; reg := a subsc reg ,#data[7:0] c, v, z, a a := reg -data[7:0]-(1-c); if underflow then c := 0 else c := 1; reg := a subsc reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg1 , reg2 c, v, z, a a := reg1 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg , eaddr c, v, z, a a := reg - dm(eaddr) -(1-c); if underflow then c := 0 else c := 1; reg := a mul reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mul reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mul reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mul reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mula reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mula reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mula reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mula reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mshl reg ,#shift[2:0] u, u, u, a a := ( reg *2 shift )[7:0]; reg := ( reg *2 shift )[15:8] mshr reg ,#shift[2:0] u, u, u, a a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] mshra reg ,#shift[2:0] u, u, u, a* a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] cmp reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) tstb reg ,#bit[2:0] -, -, z, a a[bit] := reg[bit] ; other bits in a are 0 setb reg ,#bit[2:0] -, -, z, a reg[bit] := 1; other bits unchanged; a := reg clrb reg ,#bit[2:0] -, -, z, a reg[bit] := 0; other bits unchanged; a := reg invb reg ,#bit[2:0] -, -, z, a reg[bit] := not reg[bit] ; other bits unchanged; a := reg
3-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver sflag -,-,-, a a[7] := c; a[6] := c xor v; a[5] := st full; a[4] := st empty rflag reg c, v, z, a a := reg << 1; ; a[0] := 0; c := reg[7] rflag eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] freq divn -,-,-, - reduces the cpu fr equency (divn=nodiv, div2, div4, div8, div16) halt -,-,-, - halts the cpu nop -,-,-, - no operation - = unchanged, u = undefined, *mshr reg ,# 1 doesn?t shift by 1 table 3-4. instruction short reference the coolrisc816 has 8 different addressing modes. thes e modes are described in table 3-5. in this table, the notation ix refers to one of the data memory index registers i0, i1, i2 or i3. using eaddr in an instruction of table 3-4 will acce ss the data memory at the address dm(eaddr) and will simultaneously execute the index operation. extended address eaddr accessed data memory location dm(eaddr) index operation addr[7:0] dm(h00&addr[7:0]) - direct addressing (ix) dm(ix) - indexed addressing (ix, offset[7:0]) dm(ix+offset) - indexed addressing with immediate offset (ix,r3) dm(ix+r3) - indexed addressing with register offset (ix)+ dm(ix) ix := ix+1 indexed addressing with index post-increment (ix,offset[7:0])+ dm(ix+offset) ix := ix+offset indexed addressing with index post-increment by the offset -(ix) dm(ix-1) ix := ix-1 indexed addressing with index pre-decrement -(ix,offset[7:0]) dm(ix-offset) ix := ix -offset indexed addressing with index pre-decrement by the offset table 3-5. extended address mode description eleven different jump conditions are implemented as shown in table 3-6. the contents of the column cc in this table should replace the cc notation in the instructi on description of table 3-4. cc condition cs c=1 cc c=0 zs z=1 zc z=0 vs v=1 vc v=0 ev (ev1 or ev0)=1 after cmp op1,op2 eq op1=op2 ne op1 op2 gt op1>op2 ge op1 op2 lt op1 4-1 lc02 - 1.1 ? 01 october 2002 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4 memory mapping 4.1 memory organisation 4-2 4.2 quick reference data memory register map 4-2 4.2.1 low power data registers (h0000-h0007) 4-3 4.2.2 system, clock configuration and reset configuration (h0010-h001f) 4-4 4.2.3 port a (h0020-h0027) 4-4 4.2.4 port b (h0028-h002f) 4-4 4.2.5 port d1 (h0030-h0033) 4-5 4.2.6 port d2 (h0034-h0037) 4-5 4.2.7 flash programming (h0038-003b) 4-5 4.2.8 event handler (h003c-h003f) 4-5 4.2.9 interrupt handler (h0040-h0047) 4-6 4.2.10 usrt (h0048-h004f) 4-7 4.2.11 uart (h0050-h0057) 4-7 4.2.12 counter/timer/pwm registers (h0058-h005f) 4-7 4.2.13 acquisition chain registers (h0060-h0067) 4-8 4.2.14 spi registers (h0068-h006f) 4-8 4.2.15 lcd voltage generator registers (h0070) 4-8 4.2.16 comparator registers (h0072-h0073) 4-8 4.2.17 voltage multiplier (h007c) 4-9 4.2.18 voltage level detector registers (h007e-h007f) 4-9 4.2.19 ram (h0080-h047f) 4-9 4.2.20 lcd driver (h8000-8022) 4-9
4-2 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.1 memory organisation the XE88LC02 cpu is built with harvard architecture . harvard architecture uses separate instruction and data memories. the instruction bus and data bus are also separated. the advantage of such a structure is that the cpu can get a new instruction and read/writ e data simultaneously. the circuit configuration is shown in figure 4-1. the cpu has its 16 internal registers. the instruction memory has a capacity of 8192 22-bit instructions. the data memory space has 8 low power registers, the peripheral register space, 1024 bytes of ra m and the lcd control register space. figure 4-1. memory mapping the cpu internal registers are described in the cpu chapter. a short reference of the low power registers and peripheral regist ers is given in 4.2. 4.2 quick reference data memory register map the data register map is given in the tables bel ow. a more detailed description of the different registers is given in the detailed de scription of the different peripherals. the tables give the following information: 1. the register name and register address 2. the different bits in the register 3. the access mode of the different bits (see table 4-4-1 for code description) 4. the reset source and reset value of the different bits f
4-3 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the reset source coding is given in table 4-4-2. to get a full description of the reset sources, please refer to the reset block chapter. code access mode r bit can be read w bit can be written r0 bit always reads 0 r1 bit always reads 1 c bit is cleared by writing any value c1 bit is cleared by writing a 1 ca bit is cleared after reading s special function, verify the detailed description in the respective peripherals table 4-4-1. access mode codes us ed in the register definitions code reset source glob nresetglobal cold nresetcold pconf nresetpconf sleep nresetsleep table 4-4-2. reset source coding used in the register definitions 4.2.1 low power data registers (h0000-h0007) name address 7 6 5 4 3 2 1 0 reg00 h0000 reg00[7:0] rw, 00000000, glob reg01 h0001 reg01[7:0] rw,00000000,glob reg02 h0002 reg02[7:0] rw,00000000,glob reg03 h0003 reg03[7:0] rw,00000000,glob reg04 h0004 reg04[7:0] rw,00000000,glob reg05 h0005 reg05[7:0] rw,00000000,glob reg06 h0006 reg06[7:0] rw,00000000,glob reg07 h0007 reg07[/:0] rw,0000000,glob table 4-4-3. low power data registers
4-4 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.2 system, clock configuration and reset configuration (h0010-h001f) name address 7 6 5 4 3 2 1 0 regsysctrl h0010 sleepen rw,0,cold enresetpconf rw,0,cold enbuserror rw,0,cold enresetwd rw,0,cold r0 r0 r0 r0 regsysreset h0011 sleep rw,0,glob sleepflag rc,0,cold resetbuserror rc, 0, cold resetwd rc, 0, cold resetfromporta rc, 0, cold r0 r0 r0 regsysclock h0012 cpusel rw,0,sleep r0 enextclock rw,0,cold biasrc rw,1,cold coldxtal r,1,sleep r0 enablextal rw,0,sleep enablerc rw,1,sleep regsysmisc h0013 r0 r0 r0 r0 r0 r0 output16k rw,0,sleep outputcpuck rw,0,sleep regsyswd h0014 r0 r0 r0 r0 watchdog[3:0] s,0000,glob regsyspre0 h0015 r0 r0 r0 r0 r0 r0 r0 clearlowpresca l c1r0,0,- regsysrctrim1 h001b r0 r0 r0 rcfreqrange rw,0,cold rcfreqcoarse[3:0] rw,0001,cold regsysrctrim2 h001c r0 r0 rcfreqfine[5:0] rw,00000,cold table 4-4-4. reset block and clock block registers 4.2.3 port a (h0020-h0027) name address 7 6 5 4 3 2 1 0 regpain h0020 pain[7:0] r regpadebounce h0021 padebounce[7:0] rw,00000000,pconf regpaedge h0022 paedge[7:0] rw,00000000,glob regpapullup h0023 papullup[7:0] rw,11111111,pconf regpares0 h0024 pares0[7:0] rw, 00000000, glob regpares1 h0025 pares1[7:0] rw,00000000,glob regpactrl h0026 r0 r0 r0 r0 r0 r0 r0 debfast rw,0,pconf regpasnaptorail h0027 pasnaptorail[7:0] rw,00000000,pconf table 4-4-5. port a registers 4.2.4 port b (h0028-h002f) name address 7 6 5 4 3 2 1 0 regpbout h0028 pbout[7:0] rw,00000000,pconf regpbin h0029 pbin[7:0] r regpbdir h002a pbdir[7:0] rw,00000000,pconf regpbopen h002b pbopen[7:0] rw,00000000,pconf regpbpullup h002c pbpullup[7:0] rw,11111111,pconf regpbana h002d pbana[7:0] rw,00000000,pconf table 4-4-6. port b registers
4-5 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.5 port d1 (h0030-h0033) name address 7 6 5 4 3 2 1 0 regpd1out h0030 pd1out[7:0] rw,00000000,pconf regpd1in h0031 pd1in[7:0] r regpd1dir h0032 pd1dir[7:0] rw,00000000,pconf regpd1pullup h0033 pd1snaptorail[3:0] rw,0000,pconf pd1pullup[3:0] rw,1111,pconf table 4-4-7. port d1 registers 4.2.6 port d2 (h0034-h0037) name address 7 6 5 4 3 2 1 0 regpd2out h0034 pd2out[7:0] rw,00000000,pconf regpd2in h0035 pd2in[7:0] r regpd2dir h0036 pd2dir[7:0] rw,00000000,pconf regpd2pullup h0037 pd2snaptorail[3:0] rw,0000,pconf pd2pullup[3:0] rw,1111,pconf table 4-4-8. port d2 registers 4.2.7 flash programming (h0038-003b) these four registers are used during flash pr ogramming only. refer to the flash programming algorithm documentation for more details. 4.2.8 event handler (h003c-h003f) name address 7 6 5 4 3 2 1 0 regevn h003c cntirqa rc1,0,glob cntirqc rc1,0,glob 128hz rc1,0,glob paevn[1] rc1,0,glob cntirqb rc1,0,glob cntirqd rc1,0,glob 1hz rc1,0,glob paevn[0] rc1,0,glob regevnen h003d evnen[7:0] rw,00000000,glob regevnpriority h003e evnpriority[7:0] r,11111111,glob regevnevn h003f r0 r0 r0 r0 r0 r0 evnhigh r,0,glob evnlow r,0,glob table 4-4-9. event handler registers the origin of the different events is summarised in the table below. event event source cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) paevn[1:0] port a table 4-4-10. event source description
4-6 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.9 interrupt handler (h0040-h0047) name address 7 6 5 4 3 2 1 0 regirqhig h0040 irqac rc1,0,glob 128hz rc1,0,glob irqspi rc1,0,glob cntirqa rc1,0,glob cntirqc rc1,0,glob cmpdirq rc1,0,glob uartirqtx rc1,0,glob uartirqrx rc1,0,glob regirqmid h0041 usrtcond2 rc1,0,glob urstcond1 rc1,0,glob pairq[5] rc1,0,glob pairq[4] rc1,0,glob 1hz rc1,0,glob vldirq rc1,0,glob pairq[1] rc1,0,glob pairq[0] rc1,0,glob regirqlow h0042 pairq[7] rc1,0,glob pairq[6] rc1,0,glob cntirqb rc1,0,glob cntirqd rc1,0,glob pairq[3] rc1,0,glob pairq[2] rc1,0,glob r0 r0 regirqenhig h0043 irqenhig[7:0] rw,0000000,glob regirqenmid h0044 irqenmid[7:0] rw,0000000,glob regirqenlow h0045 irqenlow[7:0] rw,0000000,glob regirqpriority h0046 irqpriority[7:0] r,11111111,glob regirqirq h0047 r0 r0 r0 r0 r0 irqhig r,0,glob irqmid r,0,glob irqlow r,0,glob table 4-4-11. interrupt handler registers the origin of the different interrupts is summarised in the table below. event event source cmpdirq low power comparators cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) pairq[7:0] port a uartirqrx uart reception uartirqtx uart transmission urstcond1 usrt condition 1 usrtcond2 usrt condition 2 vldirq voltage level detector irqac acquisition chain end of conversion interrupt irqspi spi end of reception/transmission interrupt table 4-4-12. interrupt source description
4-7 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.10 usrt (h0048-h004f) name address 7 6 5 4 3 2 1 0 regusrts1 h0048 r0 r0 r0 r0 r0 r0 r0 usrts1 s,1,glob regusrts0 h0049 r0 r0 r0 r0 r0 r0 r0 usrts0 s,1,glob regusrtcond1 h004a r0 r0 r0 r0 r0 r0 r0 usrtcond1 rc,0,glob regusrtcond2 h004b r0 r0 r0 r0 r0 r0 r0 usrtcond2 rc,0,glob regusrtctrl h004c r0 r0 r0 r0 usrtwaits0 r,0,glob usrtenwaitcond1 rw,0,glob usrtenwaits0 rw,0,glob usrtenable rw,0,glob regusrtbuffers1 h004d r0 r0 r0 r0 r0 r0 r0 usrtbuffers1 r,0,glob regusrtedges0 h004e r0 r0 r0 r0 r0 r0 r0 usrtedges0 r,0,glob table 4-4-13. usrt register description 4.2.11 uart (h0050-h0057) name address 7 6 5 4 3 2 1 0 reguartctrl h0050 uartecho rw,0,glob uartenrx rw,0,glob uartentx rw,0,glob uartxrx rw,0,glob uartxtx rw,0,glob uartbr[2:0] rw,101,glob reguartcmd h0051 selxtal rw,0,glob r0 uartrcsel[2:0] rw,000,glob uartpm rw,0,glob uartpe rw,0,glob uartwl rw,1,glob reguarttx h0052 uarttx[7:0] rw,0000000,glob reguarttxsta h0053 r0 r0 r0 r0 r0 r0 uarttxbusy r,0,glob uarttxfull r,0,glob reguartrx h0054 uartrx[7:0] r,00000000,glob reguartrxsta h0055 r0 r0 uartrxserr r,0,glob uartrxperr r,0,glob uartrxferr r,0,glob uartrxoerr rc,0,glob uartrxbusy r,0,glob uartrxfull r,0,glob table 4-14. uart register description 4.2.12 counter/timer/pwm registers (h0058-h005f) name address 7 6 5 4 3 2 1 0 regcnta h0058 countera[7:0] s,00000000,glob regcntb h0059 counterb[7:0] s,00000000,glob regcntc h005a counterc[7:0] s,00000000,glob regcntd h005b counterd[7:0] s,00000000,glob regcntctrlck h005c cntdcksel[1:0] rw,00,glob cntccksel[1:0] rw,00,glob cntbcksel[1:0] rw,00,glob cntacksel[1:0] rw,00,glob regcntconfig1 h005d cntddownup rw,0,glob cntcdownup rw,0,glob cntbdownup rw,0,glob cntadownup rw,0,glob cascadecd rw,0,glob cascadeab rw,0,glob cntpwm1 rw,0,glob cntpwm0 rw,0,glob regcntconfig2 h005e capsel[1:0] rw,00,glob capfunc[1:0] rw,00,glob pwm1size[1:0] rw,00,glob pwm0size[1:0] rw,00,glob regcnton h005f cntdextdiv rw,0,glob cntcextdiv rw,0,glob cntbextdiv rw,0,glob cntaextdiv rw,0,glob cntdenable rw,0,glob cntcenable rw,0,glob cntbenable rw,0,glob cntaenable rw,0,glob table 4-15. counter/timer/pwm register description.
4-8 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.13 acquisition chain registers (h0060-h0067) name address 7 6 5 4 3 2 1 0 regacoutlsb h0060 out[7:0] r,0,glob regacoutmsb h0061 out[15:8] r,0,glob regaccfg0 h0062 start w r0,0,glob set_nelconv[1:0] rw,01,glob set_osr[2:0] rw,010,glob cont rw,0,glob r0 regaccfg1 h0063 ib_amp_adc[1:0] rw,11,glob ib_amp_pga[1:0] rw,11,glob enable[3:0] rw,0000,glob regaccfg2 h0064 fin rw,00,glob pga2_gain[1:0] rw,00,glob pga2_offset[3:0] rw,0000,glob regaccfg3 h0065 pga1_gain rw,0,glob pga3_gain[6:0] rw,0000000,glob regaccfg4 h0066 r0 pga3_offset rw,0000000,glob regaccfg5 h0067 busy r,0,glob def w r0 amux[4:0] rw,00000,glob vmux rw,0,glob table 4-16. acquisition chain register description. 4.2.14 spi registers (h0068-h006f) name address 7 6 5 4 3 2 1 0 regspicontrol h0068 clearcounter c1 r0 notslaveselect rw,1,glob spimaster rw,1,glob spienable rw,0,glob clockphase rw,1,glob clockpolarity rw,0,glob baudrate[1:0] rw,00,glob regspistatus h0069 r0 r0 r0 r0 r0 spioverflow r c1,0,glob spirxfull r,0,glob spitxempty r w1,1,glob regspidataout h006a spidataout[7:0] rw,00000000,glob regspidatain h006b spidatain[7:0] r,00000000,glob regspipullup h006c r0 r0 r0 r0 spipullup[3:0] rw,1111,pconf regspidir h006d r0 r0 r0 r0 spidir[3:0] rw,0000,pconf table 4-17. spi register description. 4.2.15 lcd voltage generator registers (h0070) name address 7 6 5 4 3 2 1 0 regvgencfg0 h0070 r0 r0 vgenclksel[1:0] rw,10,glob vgenoff rw,1,glob vgenmode rw,0,glob vgenstdb rw,0,glob vgenrefen rw,0,glob table 4-18. lcd voltage generator register. 4.2.16 comparator registers (h0072-h0073) name address 7 6 5 4 3 2 1 0 regcmpdstat h0072 cmpdstat[3:0] rca,0000,glob cmpdout[3:0] r,0000,glob regcmpdctrl h0073 irqonrising[2:0] rw,000,glob enirqch[3:0] rw,0000,glob enable rw,0,glob table 4-19. low power comparator registers
4-9 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4.2.17 voltage multiplier (h007c) name address 7 6 5 4 3 2 1 0 regvmultcfg0 h007c r0 r0 r0 r0 r0 enable rw,0,glob fin[1:0] rw,00,glob table 4-20. vmult register. 4.2.18 voltage level detector registers (h007e-h007f) name address 7 6 5 4 3 2 1 0 regvldctrl h007e r0 r0 r0 r0 vldrange rw,0,glob vldtune[2:0] rw,000,glob regvldstat h007f r0 r0 r0 r0 r0 vldresult r,0,glob vldvalid r,0,glob vlden rw,0,glob table 4-21. voltage level detector register description 4.2.19 ram (h0080-h047f) the 1024 ram bytes can be accessed for read and writ e operations. the ram has no reset function. variables stored in the ram should be initialised befor e use since they can have any value at circuit start up. 4.2.20 lcd driver (h8000-8022) name address 7 6 5 4 3 2 1 0 reglcddata0 h8000 lcddata0[7:0] rw,00000000,pconf reglcddata1 h8001 lcddata1[7:0] rw,00000000,pconf reglcddata2 h8002 lcddata2[7:0] rw,00000000,pconf reglcddata3 h8003 lcddata3[7:0] rw,00000000,pconf reglcddata4 h8004 lcddata4[7:0] rw,00000000,pconf reglcddata5 h8005 lcddata5[7:0] rw,00000000,pconf reglcddata6 h8006 lcddata6[7:0] rw,00000000,pconf reglcddata7 h8007 lcddata7[7:0] rw,00000000,pconf reglcddata8 h8008 lcddata8[7:0] rw,00000000,pconf reglcddata9 h8009 lcddata9[7:0] rw,00000000,pconf reglcddata10 h800a lcddata10[7:0] rw,00000000,pconf reglcddata11 h800b lcddata11[7:0] rw,00000000,pconf reglcddata12 h800c lcddata12[7:0] rw,00000000,pconf reglcddata13 h800d lcddata13[7:0] rw,00000000,pconf reglcddata14 h800e lcddata14[7:0] rw,00000000,pconf reglcddata15 h800f lcddata15[7:0] rw,00000000,pconf regplcdout0 h8010 plcdout0[7:0] rw,00000000,pconf regplcdout1 h8011 plcdout1[7:0] rw,00000000,pconf
4-10 d0309-124 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver regplcdout2 h8012 plcdout2[7:0] rw,00000000,pconf regplcdout3 h8013 plcdout3[7:0] rw,00000000,pconf regplcddir0 h8014 plcddir0[7:0] rw,00000000,pconf regplcddir1 h8015 plcddir1[7:0] rw,00000000,pconf regplcddir2 h8016 plcddir2[7:0] rw,00000000,pconf regplcddir3 h8017 plcddir3[7:0] rw,00000000,pconf regplcdpullup0 h8018 plcdpullup0[7:0] rw,00000000,pconf regplcdpullup1 h8019 plcdpullup1[7:0] rw,00000000,pconf regplcdpullup2 h801a plcdpullup2[7:0] rw,00000000,pconf regplcdpullup3 h801b plcdpullup3[7:0] rw,00000000,pconf regplcdin0 h801c plcdin0[7:0] r regplcdin1 h801d plcdin1[7:0] r regplcdin2 h801e plcdin2[7:0] r regplcdin3 h801f plcdin3[7:0] r reglcdon h8020 r0 r0 r0 r0 r0 lcdsleep rw,1,glob lcdmux[1:0] rw,00,glob reglcdse h8021 lcdse3 rw,1,glob lcdse7 rw,1,glob lcdse11 rw,1,glob lcdse15 rw,1,glob lcdse19 rw,1,glob lcdse23 rw,1,glob lcdse27 rw,1,glob lcdse31 rw,1,glob reglcdclkframe h8022 lcddivfreq[2:0] rw,000,glob r0 r0 r0 lcdfreq[1:0] rw,00,glob table 4-22. lcd driver registers.
5-1 low power modes ? 1.2- 8 janvier 2001 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 5. low power modes 5.1 f eatures ............................................................................................................................... ..5-2 5.1.1 ov erview................................................................................................................. .................5-2 5.2 o perating mode ......................................................................................................................5-2
5-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 5.1 features 5.1.1 overview the xe8000 chips have three operating modes. thes e are the normal, low current and very low current modes (see figure 5-1). the different modes are controlled by the reset and clock blocks (see the documentation of the respective blocks). 5.2 operating mode start-up all bits are reset in the design when a por or padnreset is active. rc is enabled, xtal is disabled and cpu is reset (pmaddr = 0000). if the port a is used to return from the sleep mode, all bits with nresetcold do not change (see sleep mode) start-up all bits with nresetglobal and nresetpconf(if enabl ed) are reset. clock configuration doesn?t change except cpuck (freqdiv is reset, see clock block). cpu is reset active mode this is the mode where the cpu and all periphera ls can work and execute the embedded software. standby mode executing a halt instruction moves the xe8000 into the standby mode. the cpu is stopped, but the clocks remain active. therefore, the enabled peripherals remain active e.g. for time keeping. a reset or an interrupt/event request (if enabled) cancels the standby mode. sleep mode this is a very low-power mode because all circuit clocks and all peripherals are stopped. only some service blocks remain active. no time-keeping is possible. two instructions are necessary to move into sleep mode. first, the sleepen (sleep enable) bit in regsysctrl has to be set to 1. the sleep mode can then be activated by setting the sleep bit in regsysreset to 1. there are three possibe ways to wake-up from the sleep mode: 1. the por (power-on-reset caused by a power-down followed by power-on). the ram information is lost. 2. the padnreset 3. the port a reset combination (if the port a is present in the product). see port a documentation for more details. note : if the port a is used to return from the slee p mode, all bits with nresetcold do not change ( regsysctrl , regsysreset (except bit sleep ), enextclock and biasrc in regsysclock , regsysrctrim1 and regsysrctrim2 ). the sleepflag bit in regsysreset , reads back a 1 if the circuit was in sleep mode since the fl ag was last cleared (see reset block for more details). note : it is recommended to insert a nop instruction after the instruction that sets the circuit in sleep mode because this instruction can be execut ed when the sleep mode is left using the resetfromporta.
5-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver start-up reset active stand-by sleep halt instruction interrupt/event set bit sleep por padnreset porta reset por padnreset normal mode low current very low current por padnreset porta reset watchdog reset buserror reset porta reset watchdog reset por padnreset without condition without condition figure 5-1. xe8000 operating modes.
6-1 reset generator ? 1.3 ?06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 6. reset generator 6.1 features 6-2 6.2 overview 6-2 6.3 register map 6-2 6.4 reset handling capabilities 6-3 6.5 reset source description 6-4 6.5.1 power on reset 6-4 6.5.2 nreset pin 6-4 6.5.3 programmable port a input combination 6-4 6.5.4 watchdog reset 6-4 6.5.5 buserror reset 6-5 6.6 sleep mode 6-5 6.7 control register description and operation 6-5 6.8 watchdog 6-5 6.9 start-up and watchdog specifications 6-6
6-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 6.1 features ? power on reset (por) ? external reset from the nreset pin ? programmable watchdog timer reset ? programmable buserror reset ? sleep mode management product dependant: ? programmable port a input combination reset 6.2 overview the reset block is the reset manager. it handles the different reset sources and distributes them through the system. it also controls the sleep mode of the circuit. 6.3 register map register name regsysctrl regsysreset regsyswd table 6-1. reset registers table 6-1 gives the different r egisters used by this block.
6-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regsysctrl rw reset function 7 sleepen r w 0 nresetcold enables sleep mode 0: sleep mode is disabled 1: sleep mode is enabled 6 enresetpconf r w 0 nresetcold enables the nresetpconf signal when the nresetglobal is active 0: nresetpconf is disabled 1: nresetpconf is enabled 5 enbuserror r w 0 nresetcold enables reset from buserror 0: buserror reset source is disabled 1: buserror reset source is enabled 4 enresetwd r w 0 nresetcold enables reset from watchdog 0: watchdog reset source is disabled 1: watchdog reset source is enabled this bit can not be set to 0 by sw 3 ? 0 - r 0000 unused table 6-2. regsysctrl register. pos. regsysreset rw reset function 7 sleep rw 0 nresetglobal sleep mode control (reads always 0) 6 sleepflag r c 0 nresetcold sleep mode was active before 5 resetbuserror r c 0 nresetcold reset source was buserror 4 resetwd r c 0 nresetcold reset source was watchdog 3 resetfromporta r c 0 nresetcold reset source was port a combination 2 ? 0 r 000 unused table 6-3. regsysreset register pos. regsyswd rw reset function 7 - 4 - r 0000 unused wdkey[3] w watchdog key bit 3 3 wdcounter[3] r 0 nresetglobal watchdog counter bit 3 wdkey[2] w watchdog key bit 2 2 wdcounter[2] r 0 nresetglobal watchdog counter bit 2 wdkey[1] w watchdog key bit 1 1 wdcounter[1] r 0 nresetglobal watchdog counter bit 1 wdkey[0] w watchdog key bit 0 0 wdcounter[0] r 0 nresetglobal watchdog counter bit 0 table 6-4. regsyswd register 6.4 reset handling capabilities there are 5 reset sources: ? power on reset (por) ? external reset from the nreset pin ? programmable port a input combination ? programmable watchdog timer reset ? programmable buserror reset on processor access outside the allocated memory map
6-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver another reset source is the bit sleep in the regsysreset register. this source is fully controlled by software and is only used during the sleep mode. four internal reset signals are generated from these sources and distri buted through the system: ? nresetcold: is asserted on por or by the nreset pin ? nresetglobal: is asserted when nresetcold or any other enabled reset source is active ? nresetsleep: is asserted w hen the circuit is in sleep mode ? nresetpconf: is asserted when nresetglobal is active and if the enresetpconf bit in the regsysctrl register is set. this reset is generally us ed in the different ports. it allows to maintain the port configuration unchanged while the rest of the circuit is reset. table 6-5 shows a summary of the dependency of the internal reset signals on the various reset sources. in all the tables describing the different registers, the reset source is indicated. internal reset signals nresetpconf asserted reset source nresetglobal when enresetpconf is set to 0 when enrestpconf is set to 1 nresetsleep nresetcold por asserted asserted asserted asserted asserted nreset pin asserted asserted asserted asserted asserted porta input asserted - asserted - - watchdog asserted - asserted - - buserror asserted - asserted - - sleep - - - asserted - table 6-5. internal reset assertion as a function of the reset source. 6.5 reset source description 6.5.1 power on reset the power on reset (por) monitors the external supply voltage. it activates a reset on a rising edge of this supply voltage. the reset is inactivated only if the internal voltage regulator has started up. the por block performs no precise voltage level detection. 6.5.2 nreset pin applying a low input state on the nreset pin can activate the reset. 6.5.3 programmable port a input combination port a (if present in the product) can generate a re set signal. see the description of the port a for further information. 6.5.4 watchdog reset the watchdog will genera te a reset if the enresetwd bit in the regsysctrl register has been set and if the watchdog is not cleared in time by the processor. see chapter 6.8 describing the watchdog for further information.
6-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 6.5.5 buserror reset the address space is assigned as shown in the register map of the product. if the enbuserror bit in the regsysctrl register is set and the software accesses an unused address, a reset is generated. 6.6 sleep mode entering the sleep mode will reset a part of the circuit. the reset is used to configure the circuit for correct wake-up after the sleep mode. if the sleepen bit in the regsysctrl register has been set, the sleep mode can be entered by setting the bit sleep in regsysreset . during the sleep mode, the nresetsleep signal is active. for detailed in formation on the sleep mode, see the system documentation. 6.7 control register description and operation two registers are dedicated fo r reset status and control, regsysreset and regsysctrl . the bits sleep, sleepflag and sleepen are also located in those register s and are described in the chapter dedicated to the different operating mo des of the circuit (system block). the regsysreset register gives information on the source that generated the last reset. it can be read at the beginning of the applicat ion program to detect if the circui t is recovering from an error or exception condition, or if the circuit is starting up normally. ? when resetbuserror is 1, a forbidden address access generated the reset. ? when resetwd is 1, the watchdog generated the reset. ? when resetfromporta is 1, a porta combination generated the reset. note: if no bit is set to 1, the reset source was either the nreset pin or the internal por. note: several bits might be set or not, if the register was not cleared in between 2 reset occurrences. the two other bits concern the sleep mode control and information (see system documentation for the sleep mode description). ? when sleepflag is 1, the sleep mode was active before the reset occurred. this bit will always appear together with the resetfromporta bit since all other po ssibilities to leave the sleep mode (por and nreset pin) will clear the sleepflag . ? when sleep is set to 1, and sleepen is 1, the sleep mode is entered. the bit always reads back a 0. the regsysctrl register enables the different available reset sources and the sleep mode. ? enbuserror enables the reset due to a bus error condition. ? enresetwd enables the reset due to the watchdog (can not be disabled once enabled). ? enresetpconf enables the reset of the port configurations when reset by port a, a bus error or the watchdog. ? sleepen unlocks the sleep bit. as long as sleepen is 0, the sleep bit has no effect. 6.8 watchdog the watchdog is a timer, which has to be cleared at least every 2 seconds by the software to prevent a reset to be generated by the timeout condition. the watchdog can be enabled by software by setting the enresetwd bit in the regsysctrl register to 1. it can then only be disabled by a power on rese t or by setting the nreset pin to a low state.
6-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the watchdog timer can be cleared by writi ng consecutively the values hx0a and hx03 to the regsyswd register. the sequence must strictly be respected to clear the watchdog. in assembler code, the sequence to clear the watchdog is: move addrregsyswd, #0x0a move addrregsyswd, #0x03 only writing hx0a followed by hx03 resets the wd . if some other write instruction is done to the regsyswd between the writing of the hx0a and hx03 va lues, the watchdog timer will not be cleared. it is possible to read the status of the watchdog in the regsysw d register. the watchdog is a 4 bit counter with a count range between 0 and 7. the system reset is genera ted when the counter is reaching the value 8. 6.9 start-up and watchdog specifications at start-up of the circuit, the por block generates a reset signal during t por . the circuit starts software execution after this period (see system chapter). the por is intended to force the circuit into a correct state at start-up. for precise moni toring of the supply voltage, the voltage level detector (vld) has to be used. symbol parameter min typ max unit comments t por por reset duration 5 20 ms vbat_sl supply ramp up 0.5 v/ms 1 wdtime watchdog timeout period 2 s 2 table 6. electrical and timing specifications note: 1) the vbat_sl defines the minimum slope requir ed on vbat. correct start-up of the circuit is not guaranteed if this slope is too slow. in such a case, a delay has to be built using the nreset pin. note: 2) the minimal watchdog timeout period is guarant eed when the internal oscillators are used. in case an external clock source is used, the watc hdog timeout period will be correct in so far the contents of the regsysrctrim1 and regsysrctrim2 registers are correct (see clock block documentation for more details).
7-1 clock generation ? 2.4 ? 6 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 7. clock generation 7.1 f eatures ............................................................................................................................... ................7-2 7.2 o verview ............................................................................................................................... ...............7-2 7.3 r egister map ............................................................................................................................... .........7-2 7.4 i nterrupts and events map .................................................................................................................7-3 7.5 c lock sources ............................................................................................................................... ......7-5 7.5.1 rc oscillator c onfiguration .................................................................................................... ...............7-5 7.5.2 rc oscillator fr equency tuning ................................................................................................. .............7-5 7.5.3 rc oscillator sp ecifications ................................................................................................... ................7-6 7.6 x tal oscillator ............................................................................................................................... .....7-7 7.6.1 xtal config uration ............................................................................................................. .....................7-7 7.6.2 xtal oscillator specifications ................................................................................................. .................7-7 7.7 e xternal clock ............................................................................................................................... .....7-8 7.7.1 external clock configuration ................................................................................................... ...............7-8 7.7.2 external clock specification ................................................................................................... ................7-8 7.8 c lock source selection ......................................................................................................................7-8 7.9 p rescalers ............................................................................................................................... ............7-9 7.10 32 k h z frequency selector ..............................................................................................................7-10
7-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 7.1 features 3 available clock sources (rc oscillator, quartz oscillator and external clock). ? 2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). ? cpu clock disabling in halt mode. 7.2 overview the xe88lcxx chips can work on differ ent clock sources (rc os cillator, quartz oscillator and external clock). the clock generator block is in charge of distribut ing the necessary clock frequencies to the circuit. figure 7-1 represents the functi onality of the clock block. the internal rc oscillator or an exter nal clock source can be selected to drive the high prescaler. this prescaler generates frequency divisions down to 1/256 of its input frequency. a 32khz clock is generated by enabling the quartz oscillator (if present in the product) or by selecting the appropriate tap on the high prescaler. the low prescaler generates clock signals fr om 32khz down to 1hz. the clock source for the cpu can be selected from the rc oscillator, the external clock or the 32khz clock. 7.3 register map pos. regsysclock rw reset function 7 cpusel r/w 0 nresetsleep select speed for cpuck 6 - r 0 unused 5 enextclock r/w 0 nresetcold enable for external clock 4 biasrc r/w 1 nresetcold enable rcbi as (reduces start-up time of rc). 3 coldxtal r 1 nresetsleep xtal in start phase 2 - r 0 unused 1 enablextal r/w 0 nresetsleep enable xtal oscillator 0 enablerc r/w 1 nresetsleep enable rc oscillator table 7-1: regsysclock register pos. regsysmisc rw reset function 7-2 -- r 000000 unused 1 output16k r/w 0 nresetsleep output 16 khz signal on pb[3] 0 outputcpuck r/w 0 nresetsleep output cpu clock on pb[2] table 7-2: regsysmisc register pos. regsyspre0 rw reset function 7-1 -- r 0000000 unused 0 clearlowprescal w1 r0 0 write 1 to reset low prescaler, but always reads 0 table 7-3: regsyspre0 register
7-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regsysrctrim1 rw reset function 7-5 -- r 000 unused 4 rcfreqrange r/w 0 nresetcold low/high freq. range (low=0) 3 rcfreqcoarse[3] r/w 0 nresetcold rc coarse trim bit 3 2 rcfreqcoarse[2] r/w 0 nresetcold rc coarse trim bit 2 1 rcfreqcoarse[1] r/w 0 nresetcold rc coarse trim bit 1 0 rcfreqcoarse[0] r/w 1 nresetcold rc coarse trim bit 0 table 7-4: regsysrctrim1 register pos. regsysrctrim2 rw reset function 7-6 -- r 00 unused 5 rcfreqfine[5] r/w 0 nresetcold rc fine trim bit 5 4 rcfreqfine[4] r/w 0 nresetcold rc fine trim bit 4 3 rcfreqfine[3] r/w 0 nresetcold rc fine trim bit 3 2 rcfreqfine[2] r/w 0 nresetcold rc fine trim bit 2 1 rcfreqfine[1] r/w 0 nresetcold rc fine trim bit 1 0 rcfreqfine[0] r/w 0 nresetcold rc fine trim bit 0 table 7-5: regsysrctrim2 register pos. regsysptckmode rw reset function 7-1 -- r 0000000 unused 0 reserved r/w 0 nresetglobal reserved table 7-6: regsysptckmode register 7.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager ck128hz regirqhig(6) regevn(5) ck1hz regirqmid(3) regevn(1) table 7-7: interrupts and events map
7-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver rc ext div. by 2 high prescaler lo w prescaler xtal system clock ck32khz en ab le rc o r en ext clo ck enablextal and not(enextclock) en ext clo ck cpu sel cpuck ck32khz ... ck1hz ckrcext ... ckrcext/256 0 1 0 1 1 0 0 1 regsysrctrim1&2 ckrcext figure 7-1. clock block structure
7-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 7.5 clock sources 7.5.1 rc oscillator configuration the rc oscillator is always turned on and selected for cpu and system operation at power-on reset, pad nreset, and when exiting sleep mode. it c an be turned off after the xtal (qua rtz oscillator) ha s been started, after selection of the external clock or by entering sleep mode. the rc oscillator has two frequency ranges: sub-mhz (50 khz to 0.5 mh z) and above-mhz (0.5 mhz to 5 mhz). inside a range, the frequency can be tuned by software for coarse and fine adjustment. see registers regsysrctrim1 and regsysrctrim2 . bit enablerc in register regsysclock controls the propagation of the rc clock signal and the operation of the oscillator. the user can stop t he rc oscillator by resetting the bit enablerc . entering the sleep mode disables the rc oscillator. note : the rc oscillator bias can be maintained while the oscillator is disabled by setting the bit biasrc in regsysclock . this allows a faster restart of the rc oscillator at the cost of increased power consumption (see section 7.5.3). 7.5.2 rc oscillator frequency tuning the rc oscillator frequency can be set using the bits in the regsysrctrim1 and regsysrctrim2 registers. figure 7-2 shows the nominal fr equency of the rc oscillator as a function of these bits. the absolute value of the frequency for a given regi ster content may change by 35% from chip to chip due to the tolerances on the integrated capacitors and resist ors. however, the modification of the fr equency as a function of a modification of the register content is fairly precis e. this means that the curves in figure 7-2 can shift up and down but that the slope remains unchanged. the bit rcfreqrange modifies the oscillator frequ ency by a factor of 10. t he upper curve in the figure corresponds to rcfreqrange =1. the rcfreqcoarse modifies the frequency of th e oscillator by a factor ( rcfreqcoarse +1). the figure represents the frequency for 5 different values of the bits rcfreqcoarse : for each value the frequency is multiplied by 2. incrementing the rcfreqfine code, increases the fre quency by about 1.4%. the frequency of the oscillator is therefor given by: f rc =f rcmin ? (1+9 ? rcfreqrange ) ? (1+ rcfreqcoarse ) ? (1.014) rcfreqfine with f rcmin the rc oscillator fr equency if the regi sters are all 0.
7-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 0 0 0000 01 0 0 0 0 1 0 0000 1 1 0000 11 1 11 1 0 1 0 00 0 1 00000 1 1 0000 1 1 1 1 11 010000 1 00 0 0 0 1 10 0 0 0 111111 01 0 00 0 10 0 00 0 1 1 00 0 0 111111 01 0 000 1 0 0 0 00 110000 1 1 1 11 1 0 0 0 0 00 0 1000 0 1 00 0 00 1 10 0 00 11 1 1 11 01 0 000 1 0000 0 11 0 0 0 0 111 1 11 01 0 000 1 0 00 0 0 1 1 00 0 0 1 11 1 1 1 01 0 00 0 10 0 0 00 1 1 0000 1 1 1 11 1 01 0 0 0 0 1 0 0 0 00 1 1 0000 1 1 1 1 11 0000 0001 0011 0111 1111 1e+04 1e+05 1e+06 1e+07 rcfreqcoarse(3:0) nominal rc oscillator frequency [hz] rcfreqrange='1' rcfreqrange='0' rcfreqfine(5:0) rcfreqfine(5:0) figure 7-2. rc oscillator nominal frequency tuning. 7.5.3 rc oscillato r specifications sym description min typ max unit comments f rcmin lowest rc frequency 25 40 55 khz note 1 rcfreqfine fine tuning step 1.4 2.0 % rc_su startup time 30 50 us biasrc =0 3 5 us biasrc =1 psrr @ dc supply voltage tbd %/v note 2 dependence tbd %/v note 3 ? f/ ? t temperature dependence 0.1 %/ c table 7-8. rc oscillator specifications note 1: this is the frequency tolerance when all trimming code s are 0. the frequency at start-up is about twice as high. note 2: frequency shift as a function of vbat with normal regulator function. note 3: frequency shift as a function of vbat while the regulator is short-circuited to vbat. the tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the software or hardware dfll (digital frequency locked loop) which uses t he crystal oscillator as a reference frequency.
7-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 7.6 xtal oscillator 7.6.1 xtal configuration the xtal operates with an external crystal of 32?768 hz. during xtal oscillator star t-up, the first 32768 cycles are masked. the two bits enablextal and coldxtal in register regsysclock control the oscillator. at power-on reset, a pad nreset pulse or during sleep mode, enablextal is reset and coldxtal is set (xtal oscillator is not selected at start-up). the user can start xtal oscillator by setting enablextal . when the xtal oscillator starts, bit coldxtal is reset after 32768 cycles. before coldxtal is reset by the system, the xtal frequency precision is not guaranteed. the xtal osc illator can be stopped by the user by resetting bit enablextal . when the user enters into sleep mode, the xtal is stopped. 7.6.2 xtal oscillator specifications the crystal oscillator has been designed for a crystal with the specifications given in table 7-9. the oscillator precision can only be guaranteed for this crystal. symbol description min typ max unit comments fs resonance frequency 32768 hz cl cl for nominal frequency 8.2 15 pf rm motional resistance 40 100 k ? cm motional capacitance 1.8 2.5 3.2 ff c0 shunt capacitance 0.7 1.1 2.0 pf rmp motional resistance of 6 th overtone (parasitic) 4 8 k ? q quality factor 30k 50k 400k - table 7-9. crystal specifications. for safe operation, low power consumption and to meet the specified precision, careful board layout is required: keep lines xin and xout short and insert a vss line in between them. connect the crystal package to vss. no noisy or digital lines near xin or xout. insert guards where needed. respect the board specifications of table 7-10. symbol description min typ max unit comments rh_xin resistance xin-vss 10 m ? rh_xout resistance xout- vss 10 m ? rh_xin_xout resistance xin- xout 50 m ? cp_xin capacitance xin- vss 0.5 3.0 pf cp_xout capacitance xout- vss 0.5 3.0 pf cp_xin_xout capacitance xin- xout 0.2 1.0 pf table 7-10. board layout specifications.
7-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the oscillator characteristics are given in table 7-11. the characteristics are valid only if the crystal and board layout meet the specifications above. symbol description min typ max unit comments f xtal nominal frequency 32768 hz st_xtal start-up time 1 2 s fstab frequency deviation -100 300 ppm note 1 table 7-11. crystal osc illator characteristics. note 1. this gives the relative frequency deviation from nominal for a crystal with cl=8.2pf and within the temperature range -40 c to 85 c. the crystal tolerance, crystal agi ng and crystal temperature drift are not included in this figure. 7.7 external clock 7.7.1 external clock configuration the user can provide an external clock instead of the in ternal oscillators. the external provided frequency is internally divided by two. the ex ternal clock input pin is xin. the system is configured fo r external clock by bit enextclock in register regsysclock . using the bits in the registers regsysrctrim1 and regsysrctrim2 , the ck32khz clock frequency can be controlled (see section 7.10). note: when using the external clock, the xtal is not available. 7.7.2 external clock specification the external clock has to satisfy the specifications in the table below. correct behavior of the circuit can not be guaranteed if the external clock signal do es not respect the specifications below. symbol description min typ max unit comments f ext external clock frequency 8 mhz note 1 pw_1 pulse 1 width 0.06 s note 1 pw_0 pulse 0 width 0.03 20 s note 1 f ext_lv external clock frequency tbd khz note 2 pw_1_lv pulse 1 width tbd s note 2 pw_0_lv pulse 0 width tbd 20 s note 2 table 7-12. external clock specifications. note 1 . for vbat 2.4v note 2 . for vbat=vreg=1.2v 7.8 clock source selection there are three possible clock sour ces available for the cpu clock. t he rc clock is always selected after power-up, a negative pulse on nreset or after sleep mo de. the cpu clock selecti on is done with the bit cpusel in regsysclock (0= fastest clock, 1= 32 khz from xtal if enablextal =1 and enextclock = 0 else from high prescaler 32 khz output). switching from one clock source to another is glitch free.
7-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the next table summarizes the different clock configurations of the circuit: clock sources clock targets cpuck mode name enextclock enablerc enablextal cpusel =0 cpusel =1 high prescaler clock input low prescaler clock input sleep 0 0 0 off off off off xtal 0 0 1 xtal xtal off xtal rc 0 1 0 rc note 2 high presc. rc high presc. rc + xtal 0 1 1 rc note 1 and 2 xtal rc note 1 xtal external 1 x x external note 2 high presc. external high presc. table 7-13: table of clocking modes. note 1: the frequency of the rc must be higher than 100 khz when xtal is enabled in order to ensure a proper 32 khz operation. note 2: the clock rc can be divided by the value of freq in struction (see coolrisc instruction information) freq instruction cpuck nodiv rc or external div2 rc/2 or external/2 div4 rc/4 or external/4 div8 rc/8 or external/8 div16 rc/16 or external/16 note 3: switching from one clock source to another and stop ping the unused clock source must be performed using 2 move instructions to regsysclock . first select the new clock sour ce and then stop the unused one. 7.9 prescalers the clock generator block embeds two divider chains: the high prescaler and the low one. the high prescaler is made of an 8 stage dividing ch ain and the low prescaler of a 15 stage dividing chain. features: ? high prescaler can only be driven wi th rc clock or external clock (bits enablerc or enextclock have to be set, see table 7-13). ? low prescaler can be driven from the high prescale r or directly with the xtal clock when bit enablextal is set to 1 and bit enextclock is set to 0. ? bit clearlowprescal in the regsyspre0 register allows to reset synchronously the low prescaler, the low prescaler is also automatically cleared when bit enablextal is set. both dividing chains are reset asynchronously by the nresetglobal signal. ? bit coldxtal =1 indicates the xtal is in its start phase. it is active for 32768 xtal cycles after setting enablextal .
7-10 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 7.10 32 khz frequency selector a decoder is used to select from the high prescaler, t he frequency tap that is the closest to 32 khz to operate the low prescaler when the xtal is not running. in this case, the rc oscillator frequency of 35% will also be valid for the low prescaler frequency outputs. the next table shows how the rc trimming values in the regsysrctrim1 and regsysrctrim2 registers select the 32 khz frequency. the least significant bits of the rcfreqfine word are not used. in order to ensure the correct frequency selection for the low prescaler when having an external clock, a proper value must be set in the rc trim registers. the code can be selected from the table below as a function of the frequency ratio between half the frequency of t he external clock and 32khz. if the frequency is not set correctly, all timings derived from the low prescaler will be shifte d accordingly (e.g. wa tchdog frequencies) and some peripherals may no longer function correctly if the deviation from 32khz is too large (e.g. the voltage level detector).
7-11 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver rcfreqrange&rcfreqcoarse(3:0)&rcfreqfine(5:3) selected high prescaler tap default case (0?0001?000) ckrcext/2 from 0?0000?000 to 0?0000?100 ckrcext from 0?0000?101 to 0?0001?100 ckrcext/2 from 0?0001?101 to 0?0001?111 ckrcext/4 0?0010?000 ckrcext/2 from 0?0010?001 to 0?0010?110 ckrcext/4 0?0010?111 ckrcext/8 from 0?0011?000 to 0?0011?100 ckrcext/4 from 0?0011?101 to 0?0011?111 ckrcext/8 from 0?0100?000 to 0?1000?010 ckrcext/4 from 0?0100?011 to 0?0100?111 ckrcext/8 0?0101?000 ckrcext/4 from 0?0101?001 to 0?0101?110 ckrcext/8 0?0101?111 ckrcext/16 from 0?0110?000 to 0?0110?101 ckrcext/8 from 0?0110?110 to 0?0110?111 ckrcext/16 from 0?0111?000 to 0?0111?100 ckrcext/8 from 0?0111?101 to 0?0111?111 ckrcext/16 from 0?1000?000 to 0?1000?011 ckrcext/8 from 0?1000?100 to 0?1000?111 ckrcext/16 from 0?1001?000 to 0?1001?010 ckrcext/8 from 0?1001?011 to 0?1001?111 ckrcext/16 from 0?1010?000 to 0?1010?001 ckrcext/8 from 0?1010?010 to 0?1010?111 ckrcext/16 0?1011?000 ckrcext/8 from 0?1011?001 to 0?1011?110 ckrcext/16 0?1011?111 ckrcext/32 from 0?1100?000 to 0?1100?110 ckrcext/16 0?1100?111 ckrcext/32 from 0?1101?000 to 0?1101?101 ckrcext/16 from 0?1101?110 to 0?1101?111 ckrcext/32 from 0?1110?000 to 0?1110?100 ckrcext/16 from 0?1110?101 to 0?1110?111 ckrcext/32 from 0?1111?000 to 0?1111?100 ckrcext/16 from 0?1111?101 to 0?1111?111 ckrcext/32 from 1?0000?000 to 1?0000?010 ckrcext/8 from 1?0000?011 to 1?0001?010 ckrcext/16 from 1?0001?011 to 1?0010?100 ckrcext/32 from 1?0010?101 to 1?0010?111 ckrcext/64 from 1?0011?000 to 1?0011?010 ckrcext/32 from 1?0011?011 to 1?0011?111 ckrcext/64 1?0100?000 ckrcext/32 from 1?0100?001 to 1?0100?110 ckrcext/64 1?0100?111 ckrcext/128 from 1?0101?000 to 1?0101?100 ckrcext/64 from 1?0101?101 to 1?0101?111 ckrcext/128 from 10110?000 to 1?0110?011 ckrcext/64 from 1?0110?100 to 1?0110?111 ckrcext/128 from 1?0111?000 to 1?0111?010 ckrcext/64 from 1?0111?011 to 1?0111?111 ckrcext/128 from 1?1000?000 to 1?1000?001 ckrcext/64 from 1?1000?010 to 1?1000?111 ckrcext/128 1?1001?000 ckrcext/64 from 1?1001?001 to 1?1111?111 ckrcext/128 table 7-14: table of 32khz high prescaler tap decoder.
8-1 interrupt handler ? 3.2 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 8. interrupt handler 8.1 f eatures ............................................................................................................................... 8-2 8.2 o verview ............................................................................................................................... 8-2 8.3 r egister map .........................................................................................................................8-2 8.4 d etailed description ............................................................................................................8-4 8.5 i nterrupt handling software ..............................................................................................8-6
8-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 8.1 features the xe8000 chips support 24 inte rrupt sources, divided into 3 levels of priority. 8.2 overview the interrupt handler allows to manage 24 interrupt sources individually. the 24 interrupt sources are divided into 3 levels of priority: high (8 interrupt sources), mid (8 interrupt sources), and low (8 interrupt sources). those 3 levels of priority are directly mapped to those supported by the coolrisc (in0, in1 and in2; see coolrisc documentation for more information). additional functions are given that allow fast detecti on of the highest priority interrupt that has been activated. 8.3 register map register name regirqhig regirqmid regirqlow regirqenhig regirqenmid regirqenlow regirqpriority regirqirq table 8-1: irq handler registers pos. regirqhig rw reset function 7 regirqhig[7] r c1 0 nresetglobal interrupt #23 (high priority) clear interrupt #23 when 1 is written 6 regirqhig[6] r c1 0 nresetglobal interrupt #22 (high priority) clear interrupt #22 when 1 is written 5 regirqhig[5] r c1 0 nresetglobal interrupt #21 (high priority) clear interrupt #21 when 1 is written 4 regirqhig[4] r c1 0 nresetglobal interrupt #20 (high priority) clear interrupt #20 when 1 is written 3 regirqhig[3] r c1 0 nresetglobal interrupt #19 (high priority) clear interrupt #19 when 1 is written 2 regirqhig[2] r c1 0 nresetglobal interrupt #18 (high priority) clear interrupt #18 when 1 is written 1 regirqhig[1] r c1 0 nresetglobal interrupt #17 (high priority) clear interrupt #17 when 1 is written 0 regirqhig[0] r c1 0 nresetglobal interrupt #16 (high priority) clear interrupt #16 when 1 is written table 8-2: regirqhig
8-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regirqmid rw reset function 7 regirqmid[7] r c1 0 nresetglobal interrupt #15 (mid priority) clear interrupt #15 when 1 is written 6 regirqmid[6] r c1 0 nresetglobal interrupt #14 (mid priority) clear interrupt #14 when 1 is written 5 regirqmid[5] r c1 0 nresetglobal interrupt #13 (mid priority) clear interrupt #13 when 1 is written 4 regirqmid[4] r c1 0 nresetglobal interrupt #12 (mid priority) clear interrupt #12 when 1 is written 3 regirqmid[3] r c1 0 nresetglobal interrupt #11 (mid priority) clear interrupt #11 when 1 is written 2 regirqmid[2] r c1 0 nresetglobal interrupt #10 (mid priority) clear interrupt #10 when 1 is written 1 regirqmid[1] r c1 0 nresetglobal interrupt #9 (mid priority) clear interrupt #9 when 1 is written 0 regirqmid[0] r c1 0 nresetglobal interrupt #8 (mid priority) clear interrupt #8 when 1 is written table 8-3: regirqmid pos. regirqlow rw reset function 7 regirqlow[7] r c1 0 nresetglobal interrupt #7 (low priority) clear interrupt #7 when 1 is written 6 regirqlow[6] r c1 0 nresetglobal interrupt #6 (low priority) clear interrupt #6 when 1 is written 5 regirqlow[5] r c1 0 nresetglobal interrupt #5 (low priority) clear interrupt #5 when 1 is written 4 regirqlow[4] r c1 0 nresetglobal interrupt #4 (low priority) clear interrupt #4 when 1 is written 3 regirqlow[3] r c1 0 nresetglobal interrupt #3 (low priority) clear interrupt #3 when 1 is written 2 regirqlow[2] r c1 0 nresetglobal interrupt #2 (low priority) clear interrupt #2 when 1 is written 1 regirqlow[1] r c1 0 nresetglobal interrupt #1 (low priority) clear interrupt #1 when 1 is written 0 regirqlow[0] r c1 0 nresetglobal interrupt #0 (low priority) clear interrupt #0 when 1 is written table 8-4: regirqlow pos. regirqenhig rw reset function 7 regirqenhig[7] rw 0 1= enable interrupt #23 6 regirqenhig[6] rw 0 1= enable interrupt #22 5 regirqenhig[5] rw 0 1= enable interrupt #21 4 regirqenhig[4] rw 0 1= enable interrupt #20 3 regirqenhig[3] rw 0 1= enable interrupt #19 2 regirqenhig[2] rw 0 1= enable interrupt #18 1 regirqenhig[1] rw 0 1= enable interrupt #17 0 regirqenhig[0] rw 0 1= enable interrupt #16 table 8-5: regirqenhig
8-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regirqenmid rw reset function 7 regirqenmid[7] rw 0 1= enable interrupt #15 6 regirqenmid[6] rw 0 1= enable interrupt #14 5 regirqenmid[5] rw 0 1= enable interrupt #13 4 regirqenmid[4] rw 0 1= enable interrupt #12 3 regirqenmid[3] rw 0 1= enable interrupt #11 2 regirqenmid[2] rw 0 1= enable interrupt #10 1 regirqenmid[1] rw 0 1= enable interrupt #9 0 regirqenmid[0] rw 0 1= enable interrupt #8 table 8-6: regirqenmid pos. regirqenlow rw reset function 7 regirqenlow[7] rw 0 1= enable interrupt #7 6 regirqenlow[6] rw 0 1= enable interrupt #6 5 regirqenlow[5] rw 0 1= enable interrupt #5 4 regirqenlow[4] rw 0 1= enable interrupt #4 3 regirqenlow[3] rw 0 1= enable interrupt #3 2 regirqenlow[2] rw 0 1= enable interrupt #2 1 regirqenlow[1] rw 0 1= enable interrupt #1 0 regirqenlow[0] rw 0 1= enable interrupt #0 table 8-7: regirqenlow pos. regirqpriority rw reset function 7-0 regirqpriority r 11111111 code of highest priority set table 8-8: regirqpriority pos. regirqirq rw reset function 7-3 - r 00000 unused 2 irqhig r 0 one or more high priority interrupts is set 1 irqmid r 0 one or more mid priority interrupts is set 0 irqlow r 0 one or more low priority interrupts is set table 8-9: regirqirq 8.4 detailed description the coolrisc core has 3 different interrupt leve ls in0, in1 and in2 (figure 8-1). when these interrupts are triggered, the program counter (pc) is loaded with a fixed address. in case more than one interrupt occurs simultaneously, the execution order is in0, in1, in2. the masking, setting and clearing of these interrupt s can be done in the stat register (see chapter describing the cpu). the interrupt handler bundles a certain number of in terrupt sources and routes them to one of these three interrupts and provides the possibility to enable/ disable each of them individually. the definition of the interrupt sources is giv en in the memory mapping chapter. regirqhig, regirqmid, and regir qlow are 8-bit registers containing flags for the interrupt sources. those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers regirqenhig , regirqenmid or regirqenlow is set) and a rising edge is detected on the corresponding interrupt source.
8-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver once memorized, an interrupt flag can be cleared by writing a ?1? in the corresponding bit of regirqhig , regirqmid or regirqlow . writing a ?0? does not modify the flag. to definitively clear the interrupt, one has to clear the cool risc interrupt in the coolrisc stat register. all interrupts are automatically cleared after a reset. two registers are provided to facilitate the writing of interrupt serv ice software. regirqpriority contains the number of the highest priority set (its value is 0xff when no interrupt is memorized). regirqirq indicates the priority level of the currently activated interrupts. all interrupt sources are sampled by the highest frequency in the system. a cpu interruption is generated and memorized when an interrupt becomes high. between the rising edge of the interrupt on the peripheral and the rising edge on the coolrisc core, there is a latency of one clock cycle. ie2 ie1 gie in2 in1 in0 ev1 ev0 stat low priority pc=h0002 medium priority pc=h0001 high priority pc=h0003 7 6 5 4 3 2 1 0 regirqhig ? ? regirqlow regirqmid 7 6 5 4 3 2 1 0 regirqenhig interrupt sources figure 8-1. principle of the interrupt handler.
8-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 8.5 interrupt handling software this chapter describes an example of the software used for the interrupt handler. this software is present by default in the software development environments. it represents only one of several possible ways of handling the interrupts. first of all, the jump addresses are defined at the beginning of the crt0.s file. in our case, all three interrupt levels jump to the same place (defined by the _interrupt label), but this can be changed if required. ######################################################################## ## reset & interrupt vectors ######################################################################## _start: jump main_init ; reset jump _interrupt ; in1 jump _interrupt ; in2 jump _interrupt ; in0 the first thing to do when an interrupt is activated is to save the context. you have to start with saving the contents of the accumulator, then the flags and finally the internal cpu registers. you will find this part of the code in the irqcomon_xx.s file. _interrupt: ######################################################################## ## save all registers and flags ######################################################################## move -(i3), a move a, r0 sflag move -(i3), a move -(i3), ipl move -(i3), iph move -(i3), i0l move -(i3), i0h move -(i3), i1l move -(i3), i1h move -(i3), i2l move -(i3), i2h move -(i3), r0 move -(i3), r1 move -(i3), r2 move -(i3), r3 next step is to determine which interrupt is acti vated. in this case, we use the value in the regirqpriority register to determine the highest priority in terrupt that was activated. other ways can be used, especially when the priori ty order fixed in the hardware needs to be changed. you will find this part of the code in the irqcomon_xx.s file. in this example, the labels ar e used as defined for the XE88LC02. ######################################################################## ## the following lines enables the adress calculation of the interrupt ## table. where regirqpriority is the addres offset for the table. ## the regirqpriority valid values are between 0x00 until 0x017. the ## 0xff value should never exist. ######################################################################## move r0,regirqpriority calls _interrupttab ; save pc+1 in ip _interrupttab: add ipl,#0x05 ; add the offset, nb instr. before table addc iph,#0x00 ; propagate carry add ipl,r0 ; add the offset of the regirqpriority addc iph,#0x00 ; propagate carry
8-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver rets ; put ip in pc ; interrupt table jump ret_int ; regirqpriority = 0x00 jump ret_int ; regirqpriority = 0x01 jump irq_pa2 ; regirqpriority = 0x02 jump irq_pa3 ; regirqpriority = 0x03 jump irq_cntd ; regirqpriority = 0x04 jump irq_cntb ; regirqpriority = 0x05 jump irq_pa6 ; regirqpriority = 0x06 jump irq_pa7 ; regirqpriority = 0x07 jump irq_pa0 ; regirqpriority = 0x08 jump irq_pa1 ; regirqpriority = 0x09 jump irq_vld ; regirqpriority = 0x0a jump irq_1hz ; regirqpriority = 0x0b jump irq_pa4 ; regirqpriority = 0x0c jump irq_pa5 ; regirqpriority = 0x0d jump irq_usrtcond1 ; regirqpriority = 0x0e jump irq_usrtcond2 ; regirqpriority = 0x0f jump irq_uartrx ; regirqpriority = 0x10 jump irq_uarttx ; regirqpriority = 0x11 jump irq_cmpd ; regirqpriority = 0x12 jump irq_cntc ; regirqpriority = 0x13 jump irq_cnta ; regirqpriority = 0x14 jump irq_spi ; regirqpriority = 0x15 jump irq_128hz ; regirqpriority = 0x16 jump irq_ac ; regirqpriority = 0x17 the next steps are to clear the interrupt flag in the in terrupt handler, to call the specific function for the identified interrupt source and to clear the interrupt in the stat register. this code can be found in the file irqsave0_xx.s. ######################################################################## irq_ac: move regirqhig, #0x80 calls handle_irq_ac jump ret_int0 ######################################################################## irq_128hz: move regirqhig, #0x40 calls handle_irq_128hz jump ret_int0 ######################################################################## irq_spi: move regirqhig, #0x20 calls handle_irq_spi jump ret_int0 ? ret_int0: clrb stat, #2 jump ret_int finally, the context and the pc have to be restor ed. this code can be found in the irqcomon_xx.s file. ret_int: ######################################################################## ## restore all registers and flags ######################################################################## move r3, (i3)+ move r2, (i3)+ move r1, (i3)+ move r0, (i3)+ move i2h, (i3)+ move i2l, (i3)+ move i1h, (i3)+
8-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver move i1l, (i3)+ move i0h, (i3)+ move i0l, (i3)+ move iph, (i3)+ move ipl, (i3)+ rflag (i3)+ move a, (i3)+ reti ######################################################################## ## end of interrupt handlers ########################################################################
9-1 event handler ? 1.2 ? 8 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 9. event handler 9.1 f eatures ............................................................................................................................... 9-2 9.2 o verview ............................................................................................................................... 9-2 9.3 r egister map .........................................................................................................................9-2 9.4 d etailed description ............................................................................................................9-3
9-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 9.1 features the xe8000 chips support 8 event sources, divided into 2 levels of priority. 9.2 overview an event is different from an interrupt in that it does not modify the program counter (pc). events are used by two microcontroller instructions. first of all, events are useful to wake-up the microcontroller when it is in halt. the software execution then simply resumes at the instruction next to the halt in struction. the second instruction is the conditional jump on event (jev). the jump is executed if one of the event flags in the stat register is set. in all other cases, t he occurrence of an event has no effect. the event handler allows to manage 8 event source s individually. the 8 event sources are divided into 2 levels of priority: high (4 event sources) and low (4 event sources). t hose 2 levels of priority are directly mapped to those supported by the coolrisc? (ev0and in1; see coolrisc? documentation for more information). additional functions are given that allow fast detec tion of the highest priori ty event that has been activated. 9.3 register map the addresses given in table 9-1 are the default values and may be different in some products. register name regevn regevnen regevnpriority regevnevn table 9-1: evn handler registers. pos. regevn rw reset function 7 regevn[7] r c1 0 nresetglobal event #7 (high priority) clear event #7 when written 1 6 regevn[6] r c1 0 nresetglobal event #6 (high priority) clear event #6 when written 1 5 regevn[5] r c1 0 nresetglobal event #5 (high priority) clear event #5 when written 1 4 regevn[4] r c1 0 nresetglobal event #4 (high priority) clear event #4 when written 1 3 regevn[3] r c1 0 nresetglobal event #3 (low priority) clear event #3 when written 1 2 regevn[2] r c1 0 nresetglobal event #2 (low priority) clear event #2 when written 1 1 regevn[1] r c1 0 nresetglobal event #1 (low priority) clear event #1 when written 1 0 regevn[0] r c1 0 nresetglobal event #0 (low priority) clear event #0 when written 1 table 9-2: regevn
9-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regevnen rw reset function 7 regevnen[7] rw 0 nresetglobal 1= enable event #7 6 regevnen[6] rw 0 nresetglobal 1= enable event #6 5 regevnen[5] rw 0 nresetglobal 1= enable event #5 4 regevnen[4] rw 0 nresetglobal 1= enable event #4 3 regevnen[3] rw 0 nresetglobal 1= enable event #3 2 regevnen[2] rw 0 nresetglobal 1= enable event #2 1 regevnen[1] rw 0 nresetglobal 1= enable event #1 0 regevnen[0] rw 0 nresetglobal 1= enable event #0 table 9-3: regevnen pos. regevnpriority rw reset function 7-0 regevnpriority r 11111111 nresetglobal code of highest event set ff if no event present. table 9-4: regevnpriority pos. regevnevn rw reset function 7-2 - r 00000 unused 1 evnhig r 0 nresetglobal one or more high priority event is set 0 evnlow r 0 nresetglobal one or more low priority event is set table 9-5: regevnevn 9.4 detailed description the coolrisc core has 2 different event levels ev0 and ev1 (figure 9-1). the setting and clearing of these events can be done in the stat register (s ee chapter describing the cpu). the event handler bundles a certai n number of event sources and routes them to one of these two events and provides the possibility to enable/disable each of them individually. the definition of the event sources is given in the memory mapping chapter. regevn is an 8-bit register containing flags for the ev ent sources. those flags are set when the event is enabled (i.e. if the corresponding bit in the registers regevnen is set) and a rising edge is detected on the corresponding event source. once memorized, writing a ?1? in the corresponding bit of regevn clears an event flag. writing a ?0? does not modify the flag. all interrupts are automatically cleared after a reset. two registers are provided to facilitate t he writing of interrupt service software. regevnpriority contains the number of the highest event set (i ts value is 0xff when no event is memorized). regevnevn indicates the priority level of the current interrupts. all event sources are sampled by the highest frequency in the system. a cpu event is generated and memorized when an event becomes high. the 8 event sources are divided into 2 levels of priority: high (4 event sources) and low (4 event sources). those 2 levels of priority are directly mapped to those supported by the coolrisc (ev0 and ev1; s ee coolrisc documentation for more information).
9-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver ie2 ie1 gie in2 in1 in0 ev1 ev0 stat 7 6 5 4 3 2 1 0 regevn 7 6 5 4 3 2 1 0 regevnen event sources figure 9-1. event handler principle.
10-1 low power data register ? 1.0 ? 11 avril 2000 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 10. low power ram 10.1 f eatures .............................................................................................................................10 -2 10.1.1 ov erview ................................................................................................................ .............10-2 10.2 r egister map .......................................................................................................................10-2
10-2 d0309-136 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 10.1 features 10.1.1 overview in order to save power consumption, 8 8-bit regist ers are provided in page 0. these memory locations should be reserved for often-updated variables. as they are real registers and not ram, power consumption is greatly reduced. 10.2 register map pos. reg00 rw reset function 7-0 reg00 rw 0 low-power data memory 7-0 reg01 rw 0 low-power data memory 7-0 reg02 rw 0 low-power data memory 7-0 reg03 rw 0 low-power data memory 7-0 reg04 rw 0 low-power data memory 7-0 reg05 rw 0 low-power data memory 7-0 reg06 rw 0 low-power data memory 7-0 reg07 rw 0 low-power data memory table 10-1: low power ram
11-1 port a ? 1.7 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 11. port a 11.1 f eatures ..........................................................................................................................11-2 11.2 o verview ..........................................................................................................................11-2 11.3 r egister map ...................................................................................................................11-3 11.4 i nterrupts and events map .............................................................................................11-4 11.5 p ort a (pa) o peration ...................................................................................................11-4 11.6 p ort a electrical specification ....................................................................................11-6
11-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 11.1 features ? input port, 8 bits wide ? each bit can be set individually for debounced or direct input ? each bit can be set individually for pullup or not ? snap-to-rail option for each input ? each bit is an interrupt request source on the rising or falling edge ? a system reset can be generated on an input pattern ? pa[0] and pa[1] can generate two event s for the cpu, individually maskable ? pa[0] to pa[3] can be used as clock inputs for the counters/timers/pwm (product dependent) 11.2 overview porta is a general pu rpose 8 bit wide digital input port, with in terrupt capability. fi gure 11-1 shows its structure. figure 11-1: structure of port a vbat 1 0 resetfromporta 8x regpapullup regpadebounce regpain regpactrl regpaedge regpares1 regpares0 0 1 8x 1 00 01 11 10 0 interrupts events cntclocks 8 8 8 8 8 debounce 10 debfast (regpactrl(0)) 1khz 32khz 8 8 8 port a 8x regpasnaptorail vss logic 8
11-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 11.3 register map there are eight registers in port a (pa), namely regpain , regpadebounce , regpapullup , regpaedge , regpares0 , regpares1 , regpactrl and regpasnaptorail . table 11-2 to table 11-9 show the mapping of control bits and functionality of these registers register name regpain regpadebounce regpaedge regpapullup regpares0 regpares1 regpactrl regpasnaptorail table 11-1: pa registers pos. regpain rw reset description 7:0 pain[7:0] r x pad pa[7] to pa[0] input value table 11-2: regpain pos. regpadebounce rw reset description 7:0 padebounce[7:0] r w 0 nresetpconf pa[7] to pa[0] 1: debounce enabled 0: debounce disabled table 11-3: regpadebounce pos. regpaedge rw reset description 7:0 paedge[7:0] r w 0 nresetglobal pa[7] to pa[0] edge configuration 0: positive edge 1: negative edge table 11-4: regpaedge pos. regpapullup rw reset description 7:0 papullup[7:0] r w 1 nresetpconf pa[7] to pa[0] pullup enable 0: pullup disabled 1: pullup enabled table 11-5: regpapullup pos. regpares0 rw reset description 7:0 pares0[7:0] r w 0 nr esetglobal pa[7] to pa[ 0] reset configuration table 11-6: regpares0 pos. regpares1 rw reset description 7:0 pares1[7:0] r w 0 nr esetglobal pa[7] to pa[ 0] reset configuration table 11-7: regpares
11-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regpactrl rw reset description 7:1 [7:1] r 0000000 unused 0 debfast r w 0 nresetpconf 0 = slow debounce, 1 = fastdebounce table 11-8: regpactrl pos. regpasnaptorail rw reset description 7:0 pasnaptorail[7:0] rw 0 nreset pconf set snap-to-rail input on table 11-9: regpasnaptorail note : depending on the status of the enresetpconf bit in regsysctrl , regpaedge, regpadebounce and regpactrl can be reset by any of the possible system resets or only with power-on reset and nreset pad. 11.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager pa_irqbus[5] regirqmid[5] pa_irqbus[4] regirqmid[4] pa_irqbus[1] regirqmid[1] regevn[4] pa_irqbus[0] regirqmid[0] regevn[0] pa_irqbus[7] regirqlow[7] pa_irqbus[6] regirqlow[6] pa_irqbus[3] regirqlow[3] pa_irqbus[2] regirqlow[2] 11.5 port a (pa) operation the port a input status (debounced or not) can be read from regpain . debounce mode: each bit in port a can be individually debo unced by setting the corresponding bit in regpadebounce . after reset, the debounce function is disabled. after enabling the debouncer, the change of the input value is accepted only if height consecutive samples are identical. selection of the clock is done by bit debfast in register regpactrl . debfast clock filter 0 1khz 1 32khz table 10: debounce frequency selection note: the tolerance on the debounce frequency depends on the selected clock source. when the external clock is used, the pulse width will be correct if the input of the low prescaler is set to a frequency close to 32khz (see clock block documentation). pullups/snap-to-rail: different functions are possible depending on the value of the registers regpapullup and regpasnaptorail . when the corresponding bit in regpapullup is set to 0, the inputs are floating (pullup and pulldown resistors are disconnected). when the corresponding bit in regpapullup is 1 and in regpasnaptorail is 0, a pullup resistor is connect ed to the input pin. finally, when the
11-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver corresponding bit in regpapullup is 1 and in regpasnaptorail is 1, the snap-to-rail function is active. the snap-to-rail function connects a pullup or pulld own resistor to the input pin depending on the value forced on the input pin. this function can be used for instance when the input port is connected to a tristate bus. when the bus is floating, the pu llup or pulldown maintains the bus in the last low impedance state before it became float ing until another low impedance output drives the bus. it also reduces the power consumption with respect to a cl assic pullup since it selects the pullup or pulldown resistor so that it confir ms the detected input state. the state of input pin is summarized in the table below. papullup[x] pasnaptorail[x] (last) externally forced pa[x] value pa[x] pull 0 x x floating 1 0 x pullup 1 1 0 pulldown 1 1 1 pullup table 11: snap-to-rail port a starts up with the pullup resistor co nnected and the snap-to-rail function disabled. port a as an interrupt source: each port a input is an interrupt request source and can be set on rising or falling edge with the corresponding bit in regpaedge . after reset, the rising edge is selected for interrupt generation by default. the interrupt source can be debounced by setting register regpadebounce . the interrupt signals are sampled on the fastest clock in the circui t. in order to guarantee that the circuit detects the interrupt, the minimal pulse length should be 1 cycle of this clock. note: care must be taken when modifying regpaedge because this register performs an edge selection. the change of this register may result in a transition, which may be interpreted as a valid interruption. port a as an event source: the interrupt signals of the pins pa[0] and pa[1] ar e also available as event s on the event controller. port a as a clock source (product dependent): images of the pa[0] to pa[3] input ports (debounc ed or not) are available as clock sources for the counter/timer/pwm peripheral. port a as a reset source: port a can be used to generate a system reset by placing a predetermined word on port a externally. the reset is built using a logical and of the 8 pares[x] signals: resetfromporta = pareset[7] and pareset[6 ] and pareset[5] and ... and pareset[0] pareset[x] is itself a logical function of the corr esponding pin pa[x]. one of four logical functions can be selected for each pin by writing into two registers regpares0 and regpares1 as shown in table 11-12. pares1[x] pares0[x] pareset[x] 0 0 0 0 1 pa[x] 1 0 not(pa[x]) 1 1 1 table 11-12: selection bits for reset signal
11-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver a reset from port a can be inhibited by placing a 0 on both pares1[x] and pares0[x] for at least 1 pin. setting both pares1[x] and pares0[x] to 1, makes the reset independent of the value on the corresponding pin. setting both registers to hff, will reset the circuit independent from the port a input value. this makes it possible to do a reset by software. note: depending of the value of pa[0] to pa[7], changes to regpares0 and regpares1 can cause a reset. therefore it is safe to have always one (regpares0[x], regpares1[x]) equal to ?00? during the setting operations. 11.6 port a electri cal specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v r pu pull-up resistance 20 50 80 k ? cin input capacitance 2.5 pf note 1 note 1: this value is indicative only since it depends on the package. table 11-13. electrical specification
12-1 port b ? 1.4 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 12. port b 12.1 f eatures ............................................................................................................................... 12-2 12.2 o verview ............................................................................................................................... 12-2 12.3 r egister map .........................................................................................................................12-2 12.4 p ort b capabilities ...............................................................................................................12-3 12.5 p ort b analog capability .....................................................................................................12- 4 12.5.1 port b analog configuration ............................................................................................. ......12-4 12.5.2 port b analog f unction specif ication .................................................................................... ..12-5 12.6 p ort b function capability ..................................................................................................12-5 12.7 p ort b digital capabilities ...................................................................................................12-6 12.7.1 port b digita l configuration............................................................................................ .........12-6 12.7.2 port b digital f unction specification................................................................................... .....12-7 12.8 l ow power comparators .....................................................................................................12- 7
12-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 12.1 features ? input / output / analog port, 8 bits wide ? each bit can be set individually for input or output ? each bit can be set individually for open-drain or push-pull ? each bit can be set individually for pull-up or not (for input or open-drain mode) ? in open-drain mode, pull-up is not active when corresponding pad is set to zero ? the 8 pads can be connected individually to four internal analog lines (4 line analog bus) ? two internal freq. (16 khz and cpuck) can be output on pb[2] and pb[3] product dependant: ? two pwm signal can be output on pads pb[0] and pb[1] ? the synchronous serial interfac e (usrt) uses pads pb[5], pb[4] ? the uart interface uses pads pb[6] and pb[7] for tx and rx 12.2 overview port b is a multi-purpose 8 bit input/output port. in ad dition to digital behavior, all pins can be used for analog signals. each port terminal can be individua lly selected as digital input or output or as analog for sharing one of four possible analog lines. 12.3 register map table 12-1 shows the port b registers. register name regpbout regpbin regpbdir regpbopen regpbpullup regpbana table 12-1: port b registers
12-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regpbout rw reset description in digital mode description in analog mode 7 ? 0 pbout[7-0] r w 0 nresetpconf pad pb[7-0] output value analog bus selection for pad pb[7-0] table 12-2: regpbout pos. regpbin rw reset description in digital mode description in analog mode 7 ? 0 pbin[7-0] r w x pad pb[7-0] input status unused table 12-3: regpbin pos. regpbdir rw reset description in digital mode description in analog mode 7 ? 0 pbdir [7-0] r w 0 nresetpconf pad pb[7-0] di rection (0=input) analog bus selection for pad pb[7-0] table 12-4 : regpbdir pos. regpbopen rw reset description in digital mode description in analog mode 7 ? 0 pbopen[7-0] r w 0 nresetpconf pad pb[7-0] open drain (1 = open drain) unused table 12-5: regpbopen pos. regpbpullup rw reset description in digital mode description in analog mode 7 ?0 pbpullup[7] r w 1 nresetpconf pull-up for pad pb[7-0 ] (1=active) connect pad pb[7-0] on selected ana bus table 12-6: regpbpullup pos. regpbana rw reset description in digital mode description in analog mode 7 ? 0 pbana [7-0] r w 0 nresetpconf set pb[7-0] in analog mode set pb[7-0] in analog mode table 12-7: regpbana note: depending on the status of the enrespconf bit in regsysctrl , the reset conditions of the registers are different. see the reset block document ation for more details on the nresetpconf signal. 12.4 port b capabilities port b utilization (priority) name high (analog) medium (functions) low (digital) (default) pb[7] analog uart rx i/o (with pull-up) pb[6] analog uart tx i/o (with pull-up) pb[5] analog usrt s1 i/o (with pull-up) pb[4] analog usrt s0 i/o (with pull-up) pb[3] analog 16 khz i/o (with pull-up) pb[2] analog clock cpu i/o (with pull-up) pb[1] analog pwm1 counter c (c+d) i/o (with pull-up) pb[0] analog pwm0 counter a (a+b) i/o (with pull-up) table 12-8: different port b functions
12-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table 12-8 shows the different usag es that can be made of the port b wi th the order of priority. if a pin is selected to be analog, it overwrites the function and digital set-up. if the pin is not selected as analog, but a function is enabled, it overwrites the digital set-up. if neither the analog nor function is selected for a pin, it is used as an ordinary digita l i/o. this is the default configuration at start-up. note: the presence of the functions is product dependent. 12.5 port b analog capability 12.5.1 port b analog configuration port b terminals can be attached to a 4 line analog bus by setting the pbana[x] bits to 1 in the regpbana register. the other registers then define the co nnection of these 4 analog lines to the different pads of port b. these can be used to implement a simple lcd driver or a/d converter. analog switching is available only when the circuit is powered with sufficient vo ltage (see specification below). below the specified supply voltage, only voltages that are close to vss or vbat can be switched. when pbana[x] is set to 1, one pad of the port b terminals is changed from digital i/o mode to analog. the usage of the registers regpbpullup , regpbout and regpbdir define the analog configuration (see table 12-9). when pbana[x] = 1 , then pbpullup[x] connects the pin to the analog bus. pbdir[x] and pbpout[x] select which of the 4 analog lines is used. analog bus selection pbdir[x] pbout[x] pbpullup[x] pb[x] selection on 0 0 1 analog line 0 0 1 1 analog line 1 1 0 1 analog line 2 1 1 1 analog line 3 x x 0 high impedance table 12-9: selection of the analog lines with regpbdir , regpbout and regpbpullup when pbana[x] = 1 example: set the pads pb[2] and pb[5] on the analog line 3. (the values x depend on the configuration of others pads) ? apply high impedance in the analog mode (move regpbpullup,#0bxx0xx0xx) ? go to analog mode (move regpbana,#0bxx1xx1xx) ? select the analog line3 (move regpbdir,#0bxx1xx1xx and move regpbout,#0bxx1xx1xx) ? apply the analog line to the output (move regpbpullup,#0bxx1xx1xx)
12-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 12.5.2 port b analog function specification the table below defines the on-resistance of the switches between the pin and the analog bus for different conditions. the series resistance between 2 pins of port b connected to the same analog line is twice the resistance given in the table. sym description min typ max unit comments ron switch resistance 11 k ? note 1 ron switch resistance 15 k ? note 2 cin input capacitance (off) 3.5 pf note 3 cin input capacitance (on) 4.5 pf note 4 table 12-10. analog input specifications. note 1: this is the series resistance between the pad and the analog line in 2 cases 1. vbat 2.4v and the vmult peripheral is present on the circuit and enabled. 2. vbat 3.0v and the vmult peripheral is not present on the circuit. note 2: this is the series re sistance in case vbat 2.8v and the peripheral vmult is not present on the circuit. note 3: this is the input capacitance seen on the pin when the pin is not connected to an analog line. this value is indicative only since it is product and package dependent. note 4: this is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin is connected to the same analog line. this value is indicative only since it is product and package dependent. 12.6 port b function capability the port b can be used for different functions implemented by other peripherals. the description below is applicable only in so far the circuit contains these peripherals. when the counters are used to implement a pwm f unction (see the documentat ion of the counters), the pb[0] and pb[1] terminals are used as outputs (pb[0] is used if cntpwm0 in regcntconfig1 is set to 1, pb[1] is used if cntpwm1 in regcntconfig1 is set to 1) and the pwm generated values override the values written in regpbout . however, pbdir(0) and pbdir(1) are not automatically overwritten and have to be set to 1. if output16k is set in regsysmisc , the frequency is output on pb[3]. this overrides the value contained in pbout(3) . however, pbdir(3) must be set to 1. the frequency and duty cycle of the clock signal are given in figure 12-1. f max is the frequency of fastest clock present in the circuit. 1/16k 1/fmax figure 12-1. 16 khz output clock timing similarly, if outputckcpu is set in regsysmisc , the cpu frequency is output on pb[2]. this overrides the value contained in pbout(2) . however, pbdir(2) must be set to 1.
12-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 1/f2 1/f1 figure 12-2. cpu output clock timing. the timing of the cpu clock (figure 12- 2) depends on the selection of the cpusel bit in the regsysclock register and is given in table 12-11. f max is the frequency of fastest clock present in the circuit. note that the tolerance on the 32 khz depen ds on the selected clock source (see clock block documentation). cpusel f1 f2 0 f max /4 f max 1 f max 32 khz table 12-11. cpu clock timing parameters. pins pb[5] and pb[4] can be used for s1 and s0 of the usrt (see usrt documentation) when the usrtenable bit is set in regusrtctrl . the pb[5] and pb[4] then become open-drain. this overrides the values contained in pbopen(5:4) , pbout(5:4) and pbdir(5:4) . if there is no external pull-up resistor on these pins, internal pull-ups should be selected by setting pbpullup(5:4) . when s0 is an output, the pin pb[4] takes the value of usrts0 in regusrts0 . when s1 is an output, the pin pb[5] takes the value of usrts1 in regusrts1 . pins pb[6] and pb[7] can be used by the uart (see uart documentation). when uartentx in reguartctrl is set to 1, pb[6] is used as output signal tx. when uartenrx in reguartctrl is set to 1, pb[7] is used as input signal rx. this overrides the values contained in pbout(7:6) and pbdir(7:6) . 12.7 port b digital capabilities 12.7.1 port b digital configuration the direction of each bit within port b (input only or input/output) can be individually set using the regpbdir register. if pbdir[x] = 1, both the input and output buffe r are active on the corresponding port b. if pbdir[x] = 0, the corresponding port b pin is an input only and the output buffer is in high impedance. after reset (nresetpconf) port b is in input only mode (pbdir[x] are reset to 0). the input values of port b are available in regpbin (read only). reading is always direct - there is no debounce function in port b. in case of possibl e noise on input signals, a software debouncer with polling or an external hardware filter have to be re alized. the input buffer is also active when the port is defined as output and the effective value on the pin can be read back. data stored in regpbout are outputted at port b if pbdir[x] is 1. the default values after reset is low (0). when a pin is in output mode ( pbdir[x] is set to 1), the output can be a conventional cmos (push- pull) or a n-channel open-drain, driving the output only low. by default, after reset (nresetpconf) the pbopen[x] in regpbopen is cleared to 0 (push-pull). if pbopen[x] in regpbopen is set to 1 then the internal p transistor in the output buffer is el ectrically removed and the output can only be driven low ( pbout[x] =0). when pbout[x] =1, the pin is high impedance. the internal pull-up or an external pull-up resistor can be used to drive to pin high. note: because the p transistor actually exists (this is not a real open-drain output) the pull-up range is limited to vdd + 0.2v (avoid forward bias the p transistor / diode).
12-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver each bit can be set individually for pull-up or not using register regpbpullup . input is pulled up when its corresponding bit in this register is set to 1. default status after (nresetpconf) is 1, which means with pull up. to limit power consumption, pull-up re sistors are only enabled when the associated pin is either a digital input or an n-channel open-drain outpu t with the pad set to 1. in the other cases (push- pull output or open-drain output driven low), the pul l up resistors are disabled independent of the value in regpbpullup . after power-on reset, the port b is configured as an input port with pull-up. during power-on reset (see reset block documentation) however, the pin pb[1] is pulled down in stead of pulled up. once the power-on reset completed, the pin pb[1] is pu lled up, exactly as the other port b pins. the input buffer is always active, except in analog m ode. this means that the port b input should be a valid digital value at all times unless the pin is set in analog mode. violating this rule may lead to high power consumption. 12.7.2 port b digital function specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.5 pf note 1 note 1: this value is indicative only since it depends on the package. 12.8 low power comparators if the low power comparator (cmpd) peripheral is present in the circuit, the signals on the pins pb[7:4] can be used as inputs for these low powe r comparators. although the comparators are functional independent of the port b configuration, it is recommended to set the pins that are used for the cmpd in analog mode without selecting any analog lines. this is to avoid high power consumption in the digital input buffer when analog or slowly varying digital signals are applied.
13-1 port d ? 1.4 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 13. port d 13.1 features 13-2 13.2 overview 13-2 13.3 register map 13-2 13.4 port d (pd) operation 13-4 13.5 port d electrical specification 13-5
13-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 13.1 features ? input / output port, 8 bits wide ? each bit can be set individually for input or output ? pull-ups are available in input mode ? snap-to-rail option in input mode 13.2 overview port d (pd) is a general purpose 8 bit input/output digital port. figure 13-1 shows its structure. figure 13-1 : structure of portd 13.3 register map there are four registers in the port d (pd), namely regpdin , regpdout , regpddir and regpdpullup . table 13-3 to table 13-6 show the mapping of control bits and functionality of these registers. register name regpdin regpdout regpddir regpdpullup table 13-1 : pd registers regpdpullup[3:0] regpdpullup[7:4] logic vbat vss regpdin regpdout regpddir 4 4 8 8 8
13-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regpdin rw reset description 7:0 pdin[7:0] r - pad pd[7:0] input value table 13-2 : regpdin pos. regpdout rw reset description 7:0 pdout[7:0] r w 0 nresetpconf pad pd[7:0] output value table 13-3 : regpdout pos. regpddir rw reset description 7:0 pddir[7:0] r w 0 nresetpconf pad pd[7:0] direction (0=input) table 13-4 : regpddir pos. regpdpullup rw reset description 7 pdsnaptorail[3] r w 1 nresetpconf snap-to-rail for pad pd[7] and pd[6] (1=active) 6 pdsnaptorail[2] r w 1 nresetpconf snap-to-rail for pad pd[5] and pd[4] (1=active) 5 pdsnaptorail[1] r w 1 nresetpconf snap-to-rail for pad pd[3] and pd[2] (1=active) 4 pdsnaptorail[0] r w 1 nresetpconf snap-to-rail for pad pd[1] and pd[0] (1=active) 3 pdpullup[3] r w 1 nresetpconf pullup for pad pd[7] and pd[6] (1=active) 2 pdpullup[2] r w 1 nresetpconf pullup for pad pd[5] and pd[4] (1=active) 1 pdpullup[1] r w 1 nresetpconf pullup for pad pd[3] and pd[2] (1=active) 0 pdpullup[0] r w 1 nresetpconf pullup for pad pd[1] and pd[0] (1=active) table 13-5 : regpdpullup
13-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 13.4 port d (pd) operation the direction of each pin of port d (input or input/output) can be individually set by using the regpddir register. if pddir[x] = 1, the output buffer on the corres ponding port d pin is enabled. after reset, port d is in input only mode ( pddir[x] are reset to 0). the input buffer is always enabled independently from the regpddir contents. output data: data are stored in regpdout prior to output at port d. input data: the status of port d is available in regpdin (read only). reading is always direct - there is no digital debounce function associated with port d. in case of possible noise on input signals, a software debouncer or an external filter must be realised. pull-up/snap to rail: when configured as an input ( pddir[x] =0), pull-ups are available on every pin. the pull-up function of the pins is controlled two by two by the pdpullup and pdsnaptorail bits in the register regpdpullup . when a bit pdpullup[x] is 0, the pull-ups on the pins pd[2x] and pd[2x+1] are disabled. when a bit pdpullup[x] is set to 1 and the bit pdsnaptorail[x] is set to 0, the pull-up resistor is connected to the pins pd[2x] and pd[2x+1]. when both pdpullup[x] and pdsnaptorail[x] are 1, the snap-to-rail function is acti ve on the pins pd[2x] and pd[2x+1]. the snap-to-rail function connects a pullup or pulld own resistor to the input pin depending on the value forced on the input pin. this function can be used for instance when the input port is connected to a tristate bus. when the bus is floating, the pu llup or pulldown maintains the bus in the last low impedance state before it became fl oating until another low impedance output is driving the bus. it also reduces the power consumption with respect to a classic pullup since it selects the pullup or pulldown resistor so that it c onfirms the detected input state. the function is summarised in the table below as a function of the different register settings. pddir[2x(+1)] pdpullup[x] pdsnaptorail[x] (last) externally forced pd[2x(+1)] value pd[2x(+1)] pull resistor 1 x x x not connected 0 0 x x not connected 0 1 0 x pullup 0 1 1 0 pulldown 0 1 1 1 pullup table 13-6: snap-to-rail and pullup function at power-on reset, port d is configured as an input port with all pull-ups active.
13-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 13.5 port d electri cal specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.0 pf note 1 note 1: this value is indicative only since it depends on the package. table 13-7. port d electrical specification
14-1 universal asynchronous receiver/ tra nsmitter ? 1.1 ? 10 novembre 2000 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 14. universal asynchronous receiver/transmitter (uart) 14.1 f eatures .............................................................................................................................14 -2 14.2 o verview ............................................................................................................................14- 2 14.3 r egisters map ....................................................................................................................14-2 14.4 i nterrupts map ...................................................................................................................14-3 14.5 u art baud rate selection .................................................................................................14-3 14.6 u art on the rc oscillator or external clock source ..................................................14-4 14.7 u art on the crystal oscillator .......................................................................................14-4 14.8 f unction description ........................................................................................................14- 5 14.8.1 configur ation bits ...................................................................................................... ..........14-5 14.8.2 transmission............................................................................................................ ...........14-5 14.8.3 reception ............................................................................................................... .............14-6 14.8.4 interrupt or polling .................................................................................................... ...........14-7 14.9 s oftware hints ..................................................................................................................14-7
14-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 14.1 features ? full duplex operation with buffered receiver and transmitter. ? internal baudrate generator with 10 programmable baudrates (300 - 153600). ? 7 or 8 bits word length. ? even, odd, or no-parity bit generation and detection ? 1 stop bit ? error receive detection: start, parity, frame and overrun ? receiver echo mode ? 2 interrupts (receive full and transmit empty) ? enable receive and/or transmit ? invert pad rx and/or tx 14.2 overview the uart pins are pb[7], which is used as rx - receive and pb[6] as tx - transmit. 14.3 registers map register name reguartctrl reguartcmd reguarttx reguarttxsta reguartrx reguartrxsta table 14-1: uart registers pos. reguartcmd rw reset description 7 selxtal r/w 0 nresetglobal select i nput clock: 0 = rc/external, 1 = xtal 6 - r 0 unused 5-3 uartrcsel(2:0) r/w 000 nreset global rc prescaler selection 2 uartpm r/w 0 nresetglobal select parity mode: 1 = odd, 0 = even 1 uartpe r/w 0 nresetglobal enable parity: 1 = with parity, 0 = no parity 0 uartwl r/w 1 nresetglobal select word length: 1 = 8 bits, 0 = 7 bits table 14-2: reguartcmd pos. reguartctrl rw reset description 7 uartecho r/w 0 nresetglobal enable echo mode: 1 = echo rx->tx, 0 = no echo 6 uartenrx r/w 0 nresetglob al enable uart reception 5 uartentx r/w 0 nresetglobal enable uart transmission 4 uartxrx r/w 0 nresetglobal invert pad rx 3 uartxtx r/w 0 nresetglobal invert pad tx 2-0 uartbr(2:0) r/w 101 nresetglobal select baud rate table 14-3: reguartctrl
14-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. reguarttx rw reset description 7-0 uarttx r/w 00000000 nresetglobal data to be send table 14-4: reguarttx pos. reguarttxsta rw reset description 7-2 - r 000000 unused 1 uarttxbusy r 0 nresetglobal uart busy transmitting 0 uarttxfull r 0 nresetglobal reguarttx full set by writing to reguarttx cleared when transferring reguarttx into internal shift register table 14-5: reguarttxsta pos. reguartrx rw reset description 7-0 uartrx r 00000000 nresetglobal received data table 14-6: reguartrx pos. reguartrxsta rw reset description 7-6 - r 00 unused 5 uartrxserr r 0 nresetglobal start error 4 uartrxperr r 0 nresetglobal parity error 3 uartrxferr r 0 nresetglobal frame error 2 uartrxoerr r/c 0 nres etglobal overrun error cleared by writing reguartrxsta 1 uartrxbusy r 0 nresetglob al uart busy receiving 0 uartrxfull r 0 nresetglobal reguartrx full cleared by reading reguartrx table 14-7: reguartrxsta 14.4 interrupts map interrupt source default mapping in the interrupt manager irq_uart_tx irqhig(1) irq_uart_rx irqhig(0) table 14-8: interrupts map 14.5 uart baud rate selection in order to have correct baud rates, the uart inte rface has to be fed with a stable and trimmed clock source. the clock source can be an external clock s ource, the rc oscillator or the crystal oscillator. the precision of the baud rate will depend on t he precision of the selected clock source.
14-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 14.6 uart on the rc oscillator or external clock source to select the external clock or rc oscillator for the uart, the bit selxtal in reguartcmd has to be 0. the choice between the rc osc illator and the external clock s ource is made with the bit enextclock in regsysclock . in order to obtain a correct baud rate, the rc oscilla tor or external clock frequency have to be set to one of the frequencies given in the table below. the precision of the obtained baud rate is directly proportional to the frequency deviation of the used cloc k source with respect to the values in the table below. frequency selection for correct uart baud rates rc oscillator (hz) external clock (hz) 2?457?600 4?915?200 1?228?800 2?457?600 614?400 1?228?800 307?200 614?400 153?600 307?200 76?800 153?600 table 14-9a for each of these frequencies, the baud rate can be selected with the bits uartbr(2:0) in reguartctrl and uartrcsel(2:0) in reguartcmd as shown in table 14-9. rc frequency (hz) 2457600 1228800 614400 307200 153600 76800 external clock freq. (hz) 4915200 2457600 1228800 614400 307200 153600 uartrcsel uartbr 111 153600 76800 38400 19200 9600 4800 110 76800 38400 19200 9600 4800 2400 101 38400 19200 9600 4800 2400 1200 100 19200 9600 4800 2400 1200 600 011 9600 4800 2400 1200 600 300 010 4800 2400 1200 600 300 - 001 2400 1200 600 300 - - 000 000 1200 600 300 - - - 001 600 300 - - - - 010 000 300 - - - - - table 14-9: uart baud rate with rc clock or external clock note 1 : although not documented here, the coding of t he baud rate used in the circuits xe88lc01, xe88lc03 and xe88lc05 can also be used. note 2 : the precision of the baud rate is directly pro portional to the frequency deviation of the used clock from the ideal frequency given in the table. in order to increase the precision and stability of the rc oscillator, the dfll (digital frequency locked l oop) can be used with the crystal oscillator as a reference. 14.7 uart on the crystal oscillator in order to use the crystal oscillator as the clock source fo r the uart, the bit selxtal in reguartcmd has to be set. the crystal oscillator has to be enabled by setting the enablextal bit in regsysclock . the baud rate selection is done using the uartbr bits as shown in table 14-10.
14-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver xtal freq. (hz) 32768 uartbr 011 2400 010 1200 001 600 000 300 table 14-10: uart baud rate with xtal clock due to the odd ratio between the crystal oscilla tor frequency and the baud rate, the generated baud rate has a systematic error of ?2.48%. 14.8 function description 14.8.1 configuration bits the configuration bits of the uart serial interface can be found in the registers reguartcmd and reguartctrl . the bit selxtal is used to select the clock source (see chapter 14.5). the bits uartselrc and uartbr select the baud rate (see chapter 14.5). the bits uartenrx and uartentx are used to enable or disable the reception and transmission. the word length (7 or 8 data bits) can be chosen with uartwl . a parity bit is added during transmission or checked during reception if uartpe is set. the parity mode (odd or even) can be chosen with uartpm . setting the bits uartxrx and uartxtx inverts the rx respectively tx signals. the bit uartecho is used to send the received data automat ically back. the transmission function becomes then: tx = rx xor uartxrx xor uartxtx . 14.8.2 transmission in order to send data, the transmitter has to be enabled by setting the bit uartentx . data to be sent have to be written to the register reguarttx . the bit uarttxfull in reguarttxsta then goes to 1, indicating to the transmitter that a new word is available. as soon as the transmitter has finished sending the previous word, it then lo ads the contents of the register reguarttx to an internal shift register and clears the uarttxfull bit. an interrupt is generated on irq_uart_tx at t he falling edge of the uarttxfull bit. the bit uarttxbusy in reguarttxsta shows that the transmitter is busy transmitting a word. a timing diagram is shown in figure 14-1. data is sent lsb first. new data should be written to the register reguarttx only while uarttxbusy is 0, otherwise data will be lost.
14-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver as y nchronous transmission w rite to re g uarttx re g uarttx word 1 reguarttx_shift word 1 shift clock tx start b0 b1 b6/7 parity stop uarttxbus y uarttxfull irq_uart_tx as y nchronous transmission ( back to back ) word 1 word 2 w rite to re g uarttx re g uarttx word 1 word 2 reguarttx_shift word 1 word 2 shift clock tx start b0 b6/7 stop start uarttxbus y uarttxfull irq_uart_tx figure 14-1. uart transmission timing diagram. 14.8.3 reception on detection of the start bit, the uartrxbusy bit is set. on detection of the stop bit, the received data are transferred from the internal shift register to the register reguartrx . at the same time, the uartrxfull bit is set and an interrupt is generated on ir q_uart_rx. this indicates that new data is available in reguartrx . the timing diagram is shown in figure 14-2. the uartrxfull bit is cleared when reguartrx is read. if the register was not read before the receiver transfers a new word to it, the bit uartrxoerr (overflow error) is set and the previous contents of the register are lost. uartrxoerr is cleared by writing any data to reguartrxsta . the bit uartrxserr is set if a start error has been detect ed. the bit is updated at data transfer to reguartrx . the bit uartrxperr is set if a parity error has been detected, i.e. the received parity bit is not equal to the calculated parity of the received dat a. the bit is updated at data transfer to reguartrx . the bit uartrxferr in reguartrxsta shows that a frame error has been detected. no stop bit has been detected.
14-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver asynchronous reception read of reguartrx (software) reguartrx_shift word 1 reguartrx word 1 shift clock rx start b0 b6/7 parity stop uartrxbusy uartrxfull irq_uart_rx figure 14-2. uart reception timing diagram. 14.8.4 interrupt or polling the transmission and reception software can be driv en by interruption or by polling the status bits. interrupt driven reception: each time an irq_uart_rx in terrupt is generated, a new word is available in reguartrx . the register has to be read before a new word is received. interrupt driven transmission: each time the contents of reguarttx is transferred to the transmission shift register, an irq_uart_tx interrupt is generated. a new word can then be written to reguarttx . reception driven by polling: the uartrxfull bit is to be read and checked. when it is 1, the reguartrx register contains new data and has to be read before a new word is received. transmission driven by polling: the uarttxfull bit is to read and checked. when it is 0, the reguarttx register is empty and a new word can be written to it. 14.9 software hints example of program for a transmission with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. wait untill the uarttxfull bit in reguarttxsta register equals 0. 4. jump to 2 to writing the next byte if the message is not finished. 5. end of transmission. example of program for a transmission with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. after an interrupt and if the message is not finished, jump to 2 4. end of transmission.
14-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver example of program for a reception with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. wait until the uartrxfull bit in the reguartrxsta register equals 1. 3. read the reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception. example of program for a reception with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. when there is an interrupt, jump to 3 3. read reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception.
15-1 universal synchronous receiver/t ransmitter ? 1.0 ? 11 mai 2000 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 15. universal synchronous receiver/transmitter (urst) 15.1 f eatures ............................................................................................................................... ................15-2 15.2 o verview ............................................................................................................................... ...............15-2 15.3 r egister map ............................................................................................................................... .........15-2 15.4 i nterrupts map ............................................................................................................................... ......15-4 15.5 c onditional edge detection 1.............................................................................................................15-4 15.6 c onditional edge detection 2.............................................................................................................15-4 15.7 i nterrupts or polling .........................................................................................................................15-5 15.8 f unction description ..........................................................................................................................15-5
15-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 15.1 features the usrt implements a hardware support fo r software implemented serial protocols: ? control of two external lines s0 and s1 (read/write). ? conditional edge detection generates interrupts. ? s0 rising edge detection. ? s1 value is stored on s0 rising edge. ? s0 signal can be forced to 0 after a falling edge on s0 for clock stretching in the low state. ? s0 signal can be stretched in the low state after a falling edge on s0 and after a s1 conditional detection. 15.2 overview the usrt block supports software universal synchr onous receiver and transmitter mode interfaces. external lines s0 and s1 respectively correspond to cl ock line and data line. s0 is mapped to pb[4] and s1 to pb[5] when the usrt block is enabled. it is independent of regpbdir (port b can be input or output). when usrt is enabled, the configurations in port b for pb[4] and pb[5] are overwritten by the usrt configuration. internal pull-ups can be used by setting the pbpullup[5:4] bits. conditional edge detections are provided. regusrts1 can be used to read the s1 data line from pb[5] in receive mode or to drive the output s1 line pb[5] by writing it when in transmit mode. it is adv ised to read s1 data when in receive mode from the regusrtbuffers1 register, which is the s1 value sampled on a rising edge of s0. 15.3 register map register name regusrts1 regusrts0 regusrtctrl regusrtcond1 regusrtcond2 regusrtbuffers1 regusrtedges0 table 15-1: usrt registers block configurat ion registers: pos. regusrts1 rw reset function 7-1 ?0000000? r - unused 0 usrts1 r/w 1 nresetglobal write: data s1 written to pad pb[5]), read: value on pb[5] (not usrts1 value). table 15-2: regusrts1
15-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regusrts0 rw reset function 7-1 ?0000000? r - unused 0 usrts0 r/w 1 nresetglobal write: clock s0 written to pad pb[4], read: value on pb[4] (not usrts0 value). table 15-3: regusrts0 the values that are read in the registers regusrts1 and regusrts0 are not necessarily the same as the values that were written in the register. the read value is read back on the circuit pins not in the registers themselves. since the outputs are open dr ain, an external circuit on the circ uit pins may force a value different from the register value. pos. regusrtctrl rw reset function 7-4 ?0000? r - unused 3 usrtwaits0 r 0 nresetglobal clo ck stretching flag (0=no stretching), cleared by writing regusrtbuffers1 2 usrtenwaitcond1 r/w 0 nresetglobal enable stretching on usrtcond1 detection (0=disable) 1 usrtenwaits0 r/w 0 nresetglobal e nable stretching operation (0=disable) 0 usrtenable r/w 0 nresetglobal enable usrt operation (0=disable) table 15-4: regusrtctrl pos. regusrtcond1 rw reset function 7-1 ?0000000? r - unused 0 usrtcond1 r/c 0 nresetglobal state of condition 1 detection (1 =detected), cleared when written. table 15-5: regusrtcond1 pos. regusrtcond2 rw reset function 7-1 ?0000000? r - unused 0 usrtcond2 r/c 0 nresetglobal state of condition 2 detection (1 =detected), cleared when written. table 15-6: regusrtcond2 pos. regusrtbuffers1 rw reset function 7-1 ?0000000? r - unused 0 usrtbuffers1 r 0 nresetglobal val ue on s1 at last s0 rising edge. table 15-7: regusrtbuffers1 pos. regusrtedges0 rw reset function 7-1 ?0000000? r - unused 0 usrtedges0 r 0 nresetglobal st ate of rising edge detection on s0 (1=detected). cleared by reading regusrtbuffers1 table 15-8: regusrtedges0
15-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 15.4 interrupts map interrupt source default mapping in the interrupt manager irq_cond2 regirqmid(7) irq_cond1 regirqmid(6) table 15-9: interrupts map 15.5 conditional edge detection 1 s1 s0 figure 15-1: condition 1 condition 1 is satisfied when s0=1 at the falling edge of s1. the bit usrtcond1 in regusrtcond1 is set when the condition 1 is detected and the usrt interface is enabled ( usrtenable =1). condition 1 is asserted for both modes (receiver and transmitter). the usrtcond1 bit is read only and is cleared by all reset conditions and by writing any data to its address. condition 1 occurrence also generates an interrupt on irq_cond1. 15.6 conditional edge detection 2 s1 s0 figure 15-2: condition 2 condition 2 is satisfied when s0=1 at the rising edge of s1. the bit usrtcond2 in regusrtcond2 is set when the condition 2 is detected and the usrt interface is enabled. condition 2 is asserted for both modes (receiver and transmitter). the usrtcond2 bit is read only and is cleared by all reset conditions and by writing any data to its address. condition 2 occurrence also generates an interrupt on irq_cond2.
15-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 15.7 interrupts or polling in receive mode, there are two possibilities to detect c ondition 1 or 2: the detection of the condition can generate an interrupt or the registers can be polled (reading and checking the regusrtcond1 and regusrtcond2 registers for the status of usrt communication). 15.8 function description the bit usrtenable in regusrtctrl is used to enable the usrt inte rface and controls the pb[4] and pb[5] pins. this bit puts these two port b lines in the open drai n configuration requested to use the usrt interface. if no external pull-ups are added on pb[4] and pb[5], the user can activate internal pull-ups by setting pbpullup[4] and pbpullup[5] in regpbpullup . the bits usrtenwaits0 , usrtenwaitcond1 , usrtwaits0 in regusrtctrl are used for transmitter/receiver control of usrt interface. figure 15-3 shows the unconditi onal clock stretching function which is enabled by setting usrtenwaits0. s0 us r tw ai ts 0 write reg usrtbuffers1 figure 15-3: s0 stretching (usrtenwaits0=1) when usrtenwaits0 is 1, the s0 line will be maintained at 0 after its falling edge (clock stretching). usrtwaits0 is then set to 1, indicating that the s0 line is forced low. one can release s0 by writing to the regusrtbuffers1 register. the same can be done in combination with condition 1 detection by setting the usrtenwaitcond1 bit. figure 15-4 shows the conditional clock stretching function, which is enabled by setting usrtenwaitcond1 .
15-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver s0 us r tw ai ts 0 write reg usrtbuffers1 s1 figure 15-4: conditional stre tching (usrtenwaitcond1=1) when usrtenwaitcond1 is 1, the s0 signal will be stretched in its low state after its falling edge if the condition 1 has been detected before ( usrtcond1 =1). usrtwaits0 is then set to 1, indicating that the s0 line is forced low. one can release s0 by writing to the regusrtbuffers1 register. figure 15-5 shows the sampling function implemented by the usrtbuffers1 bit. the bit usrtbuffers1 in regusrtbuffers1 is the value of s1 sampled on pb[4] at the last rising edge of s0. the bit usrtedges0 in regusrtedges0 is set to one on the same s0 rising edge and is cleared by a read operation of the regusrtbuffers1 register. the bit therefor indicates that a new value is present in the regusrtbuffers1 which was not yet read. s0 usrtbuffers1 read reg usrtbuffers1 s1 us r t edg e s 0 figure 15-5: s1 sampling
16-1 serial peripheral interface ? 1.3 ? 21 septe mbre 2001 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 16 serial peripheral interface 16.1 f eatures ............................................................................................................................... ..16-2 16.2 o verview ............................................................................................................................... ..16-2 16.3 r egister map ..........................................................................................................................16-2 16.4 i nterrupts map .......................................................................................................................16-4 16.5 f unction description .............................................................................................................16-4 16.5.1 spi in terface ........................................................................................................... .................16-4 16.5.1.1 general operat ion..................................................................................................... .............................. 16-4 16.5.1.2 master/slave synchronization.......................................................................................... ....................... 16-6 16.5.1.3 softwa re hints........................................................................................................ ................................. 16-7 16.5.2 general pu rpose port.................................................................................................... ...........16-8
16-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 16.1 features the spi block implements the following functionality?s: ? full duplex operating mode. ? master or slave configuration capability. ? separate transmissions data, shift data and receive data registers in order to perform back-to-back transmissions. ? four master mode frequencies av ailable to generate serial clock. ? serial clock with programmable polarity and phase. ? one enabled interrupt: spi receive register full. ? overflow detection flag. ? 4 i/o dedicated pads with 8ma drive and pull-up programmable. ? multi-slave confi guration capability. ? general purpose 4 bit wide digital input/output port mode. 16.2 overview the spi can communicate with other external spi dev ices. it provides flexibility to communicate with different spi compatible circuits from several ma nufacturers (serial eeproms, display drivers, a/d converters, audio device). four dedicated input or output pads are attached to the spi block: miso, mosi, sck, nss. six registers are used to run the spi block. regspicontrol , regspistatus , regspidataout , regspidatain , regspipullup , regspidir are used to configure the communication settings, read the flags, write and read the exchanged data, and for the pad settings. the spi device can also be used as a 4 bit general purpose input/output port. 16.3 register map register name regspicontrol regspistatus regspidataout regspidatain regspipullup regspidir table 16-1: address mapping for spi when the peripheral is used as a general-purpose parallel i/o port, the spi pads are mapped in the registers as follows ( regspidataout , regspidatain , regspipullup and regspidir ): spi pad names spi register bits nss 3 mosi 2 miso 1 sck 0 table 16-2: pin mapping in general purpose port mode
16-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver block configurat ion registers: pos. regspicontrol rw reset function 7 clearcounter w1 - writing 1 clears transmission control counters. 6 notslaveselect r/w 1 nresetglobal in master mode, this bit drives the nss output pad. unused in slave mode. it must be asserted (to 0) during a byte transfer. 5 spimaster r/w 1 nresetglobal 0: spi slave mode. 1: spi master mode. 4 spienable r/w 0 nresetglobal peripheral configuration: 0: general purpose digital i/o port 1: spi interface 3 clockphase r/w 1 nresetglobal controls the timing relationship between the serial clock and spi data (cf. figure 16-2 and figure 16-3). 2 clockpolarity r/w 0 nresetglobal determ ines the idle-state of the spi clock signal (cf. figure 16-2 and figure 16-3). 1-0 baudrate r/w 00 nresetglobal selects the baud rate in master mode. 00 => ckrcext/2 01 => ckrcext/8 10 => ckrcext/16 11 => 4khz table 16-3: regspicontrol note that the precision of the 4khz depends on the selected clock source (see documentation of the clock block). in slave mode, the fastest clock of the ci rcuit should be at least 4 times faster than the baud rate of the master. pos. regspistatus rw reset function 7-3 -- r 00000 unused 2 spioverflow r c1 0 nresetglobal this flag is set when a new byte is loaded in spidatain before the previous byte was read. writing 1 clears the flag. 1 spirxfull r 0 nresetglobal this flag is set each time a byte transfers from the shift register to spidatain . it is cleared by reading spidatain . 0 spitxempty r w1 1 nresetglobal this flag is cleared each time the cpu writes a byte in spidataout . it is set when a byte transfers from spidataout to the shift register. in the master mode, writing 1 to this bit performs the data transfer spidataout to the shift register and enables the start of transmission. in the slave mode, the byte transfer is done automatically except for the very first byte after nresetglobal (cf.16.6 software hints). table 16-4: regspistatus pos. regspidataout rw reset function 7-0 spidataout[7:0] r/w 00000000 nresetglobal spi mode: transmission data buffer i/o mode: output data (only bits 3:0, see table 16-2) table 16-5: regspidataout
16-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regspidatain rw reset function 7-0 spidatain[7:0] r 00000000 nresetglobal spi mode: reception data byte i/o mode: input data (only bits 3:0, see table 16-2, bits 7:4 read 0) table 16-6: regspidatain pos. regspipullup rw reset function 7-4 -- r 0000 unused. 3-0 spipullup r/w 1 nresetpconf pullup configuration in both spi and i/o mode (1=active). mapping as in table 16-2. table 16-7: regspipullup note that pull-ups are disconnected independent from the value in regspipullup if the corresponding pin is configured as an output. pos. regspidir rw reset function 7-4 -- r 0000 unused. 3-0 spidir[3:0] r/w 0 nresetpconf i/o mode only (mapping in table 16-2) 1: output enabled 0: output disabled table 16-8: regspidir 16.4 interrupts map interrupt source default mapping in the interrupt manager irq_spi(0) irq_bus(21) table 16-9: interrupts map irq_spi(0) interrupt is activated at the assertion of the spirxfull flag (cf. regspistatus description). 16.5 function description depending on the value of the bit spienable in the regspicontrol register, the spi peripheral can work either as a real spi interface (master or slave) or as a general purpose 4 bit wide digital input/output port. 16.5.1 spi interface 16.5.1.1 general operation the peripheral is configured as an spi by setting the bit spienable =1 in regspicontrol . the bit spimaster in regspicontrol selects the master or slave mode. the spi interface supports 4 physical wires between one master device and one or more slave devices (figure 16-1): miso (master in slave out), mosi (mas ter out slave in), sck (s erial clock), nss (slave select).
16-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver a byte transmission performs a rotate operation between the value stored in the 8 bit shift register of the master device and the value stored in the 8 bit shift r egister of the (selected) slave device. the sck line is used to synchronize both spi interfaces. the transmission format depends on the two configuration bits clockphase and clockpolarity . these 2 bits should be configured in the same way in the sl ave and the master device in order to properly run the spi transmission. the transmission baud rate depends on the two bits baudrate , these 2 bits are only used in the master device to generate the serial cl ock sck signal at the selected frequency. data are transferred in a duplex way from master to slave through the mosi wire and from slave to master through the miso wire. data are always sent most significant bit first. each spi device sequentially operates in two times: one clock edge to sample th e received bit, and the other clock edge to shift the byte inside the shift register. the nss signal is softw are controlled. it must be driven by the spi master device by writing to the bit notslaveselect in regspicontrol . nss should remain low during the byte transmission. shift register shift register baud rate generator miso miso mosi mosi sck sck nss nss master slave figure 16-1: connection of master and slave device the next figure shows the timing diagrams for a spi transmission with clockphase equal to 0. this means the active state of the serial clock sck signal occurs on the 2 nd half of the sck cycle. sck cycle sck (cpol=0) sck (cpol=1) mosi miso nss msb msb ls b ls b bit 6 bit 5 bit 5 bit 4 bit 4 bit 6 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 1 2 3 4 5 6 7 8 samp le shift samp le samp le samp le samp le samp le samp le samp le shift shift shift shift shift shift shift figure 16-2: spi transmission format with clockphase=0
16-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the next figure shows the timing diagrams for a spi transmission with clockphase equal to 1. this means the active state of the serial clock sck signal occurs on the 1 st half of the sck cycle. sck cycle sck (cpol=0) sck (cpol=1) mosi miso nss msb msb ls b ls b bit 6 bit 5 bit 5 bit 4 bit 4 bit 6 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 1 2 3 4 5 6 7 8 samp le shift samp le samp le samp le samp le samp le samp le samp le shift shift shift shift shift shift shift figure 16-3: spi transmission format with clockphase=1 note: for both cases, it is not required to toggl e the nss signal back to high and back to low between each byte transmitted. the spi interface can be operated by polling the regspistatus register or interrupt driven. the interrupt is active on reception of a new byte. in case of a multi-slave c onfiguration, any digital output pin of any parallel port can be used to select the different slaves. in some cases, it might be easier to have dc signals on these pins and to derive the timing from the single nss pin independently from the selected slave. this can be realized by combining the nss wire from the master device with signals co ming from an output port as shown in figure 16-4. pull-up resistors can be added on the input pads (miso in master mode, mosi, nss and sck in slave mode) by setting the corresponding bits in regspipullup . use table 16-2 for the correspondence between the pads and register bits. 16.5.1.2 master/slave synchronization in the master mode, a transmission is started by writing a 1 to the bit spitxempty . this automatically loads the data of the register regspidataout to the shift register and starts the clock and shifting. at the end of the transmission, the clock stops and the received data are copied to regspidatain . the bit spitxempty should not be asserted while the previous tr ansmission is still running, otherwise, the transmitted and received data will be corrupted. in slave mode, the fastest clock in the circuit should be at least 4 times faster than the baud rate of the transmission. the transmission is synchronized by t he nss input signal. while the nss signal is high, the counters controlling the transmission are reset. the reception starts at the first clock cycle after the falling edge of nss. at the end of the transmi ssion, the received data are copied to regspidatain and the contents of the register regspidataout are copied automatically to the shift register. the data in the shift register can be overwritten by writing 1 to spitxempty. this should not be done while a transmission is running, otherwise, the tr ansmitted and received da ta will be corrupted.
16-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the counters controlling the timing of the transm ission can be reset by writing a 1 to the clearcounters bit in the regspicontrol register. in master mode, it restarts a complete transmission cycle. in slave mode, it has the same effect as a rising edge of nss. this bit should be used with caution. shift register baud rate generator miso mosi sck nss shift register miso mosi sck nss slave 1 shift register shift register miso mosi sck master shift register miso mosi sck nss slave n digital output pad 3 shift register miso mosi sck nss slave 2 digital output pad 2 digital output pad 1 figure 16-4: connection of master and slaves in the case of a multi slave configuration 16.6 software hints 16.6.1 master mode the following routine must be executed by the coolrisc in order to ru n properly the spi interface in master mode: initialization 1- write regspicontrol to enable the spi interface and to co nfigure the master mode (configured by default) and communication settings. 2- write the data to send in the regspidataout register. the spitxempty flag toggles low. 3- write 1 to the spitxempty bit to load the shift register with the value inside the regspidataout register and to start the byte transmission . the spitxempty flag toggles back high. 4- write the next data to send to the regspidataout register. the spitxempty flag toggles low.
16-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver normal operation 5- wait for the end of transmission , i.e. spirxfull flag is one or the interrupt of the receiver is asserted. 6- write 1 to the spitxempty bit to load the shift register with the value inside the regspidataout register and to start the byte transmission . the spi spitxempty flag toggles back high. 7- read regspidatain . the spirxfull flag returns to 0. 8- write the next data to send in the regspidataout register. the spitxempty flag toggles low. 9- jump to 5. 16.6.2 slave mode the following routine must be executed by the coolrisc in order to ru n properly the spi interface in slave mode: initialization 1- write regspicontrol to enable the spi interface and to configure the slave mode and communication settings (as configured in the master device). 2- write the data to send in the regspidataout register. the spitxempty flag toggles low. 3- write 1 to spitxempty bit to load the shift register with the value of the regspidataout register. the spitxempty flag toggles back high. this load is only re quired for the first byte to transmit after nresetglobal. it is automatic for the following bytes. 4- write the next data to send in the regspidataout register. the spitxempty flag toggles low. normal operation 5- wait for the end of transmission , i.e. the spirxfull flag is one or the interrupt of the receiver asserted. the shift register is automatically loaded with the value inside the regspidataout register and the spitxempty flag toggles back high. 6- read regspidatain . the spirxfull flag returns to 0. 7- write the next data to send in the regspidataout register. the spitxempty flag toggles low. 8- jump to 5. 16.6.3 general purpose port. this mode is enabled when spienable value is 0 (default value). the spi dedicated pads are used as a general purpose 4 bit input/output digital port. next figure shows the structure of the spi in this mode.
16-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver vdd s pi_pullup[3:0] spi_out[3:0] spi_dir[3:0] spi_in[3:0] regspipullup regspidataout regspidir regspidatain spi figure 16-5: structure of the spi general purpose port the direction of each bit within the spi (input or input/output) can be individually set by using the regspidir register. if regspidir[x] = 1, the corresponding spi pad becomes an output. after reset ( nresetpconf ), the spi pads are in input configuration ( regspidir[x] are reset to 0). in output configuration, the data are stored in regspidataout prior to output at spi pads. in input configuration, the stat us of spi pads is available in regspiin (read only). reading is always direct ?there is no digital debounce function associated with spi pads. in case of possible noise on input signals, a software debouncer or an ex ternal filter must be realized. if a bit in regspipullup is set, the pull-up of the corresponding input pad is active. the pull-ups are disabled in output configur ation independently of the regspipullup content. by default after reset, the spi pads are configured as input ports with all pull-up s active. note that the pull-up resistors can be used for the input pads in spi mode also. next table shows the link between spi pads and spi data bits. spi pad names spi data bits nss spidataout[3] or spidatain[3] mosi spidataout[2] or spidatain[2] miso spidataout[1] or spidatain[1] sck spidataout[0] or spidatain[0] table 16-10: spi pad/bit relationship
17-1 acquisitio n chain ? 2.6 ? 06 november 2002 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17. acquisition chain 17.1 z ooming adc? f eatures ...............................................................................................17-2 17.2 o verview ..........................................................................................................................17-2 17.3 r egister map ...................................................................................................................17-2 17.4 z ooming adc? d escription ...........................................................................................17-4 17.4.1 acquisition chain.............................................................................................................. 17-4 17.4.2 peripheral re gisters .........................................................................................................17 -5 17.4.3 continuous-time vs . on-reque st ....................................................................................17-7 17.5 i nput m ultiplexers .........................................................................................................17-7 17.6 p rogrammable g ain a mplifiers .....................................................................................17-8 17.6.1 pga & adc e nabling .....................................................................................................17-10 17.6.2 pga1 ........................................................................................................................... ...17-10 17.6.3 pga2 ........................................................................................................................... ...17-10 17.6.4 pga3 ........................................................................................................................... ...17-10 17.7 adc c haracteristics ...................................................................................................17-11 17.7.1 conversion s equence ....................................................................................................17-11 17.7.2 sampling fre quency ......................................................................................................17-12 17.7.3 over-sampling ratio ......................................................................................................17-12 17.7.4 elementary conv ersions ................................................................................................17-13 17.7.5 resolution..................................................................................................................... ..17-13 17.7.6 conversion time & throughput .....................................................................................17-14 17.7.7 output code format .......................................................................................................17-14 17.7.8 power saving modes .....................................................................................................17-16 17.8 s pecifications and m easured c urves .........................................................................17-16 17.8.1 default se ttings ..............................................................................................................1 7-16 17.8.2 specifications ................................................................................................................. 17-17 17.8.3 linearity ...................................................................................................................... ....17-19 17.8.3.1 integral n on-linear ity ......................................................................................................... ............17-19 17.8.3.2 differential n on-linea rity ..................................................................................................... ...........17-22 17.8.4 noise .......................................................................................................................... ....17-23 17.8.5 gain error and o ffset error ............................................................................................17-24 17.8.6 power consum ption .......................................................................................................17-25 17.8.7 power supply reject ion ratio........................................................................................17-27 17.9 a pplication h ints ..........................................................................................................17-28 17.9.1 input impeda nce .............................................................................................................17- 28 17.9.2 pga settling or input ch annel modifi cations .................................................................17-28 17.9.3 pga gain & offset, li nearity and no ise ........................................................................17-28 17.9.4 frequency response .....................................................................................................17-29 17.9.5 power reduct ion ............................................................................................................17-2 9
17-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.1 zoomingadc? features the zoomingadc? is a complete and versatile low-power analog front- end interface typically intended for sensing applications. the ke y features of the zoomingadc? are: programmable 6 to 16-bit dynamic range oversampled adc ? flexible gain programming between 0.5 and 1000 ? flexible and large range offset compensation ? 4-channel differential or 8-channel single-ended input multiplexer ? 2-channel differential reference inputs ? power saving modes ? direct interfacing to coolrisc? microcontroller 17.2 overview pga1 pga2 pga3 adc mux mux gd1 gd2 gd3 off2 off3 0 1 2 3 4 5 6 7 0 1 2 3 analog inputs 16 v in f s v ref v in,adc gain1 gain2 gain3 offset3 offset2 reference selection input selection zoom reference inputs v d1 v d2 f s figure 17-1. zoomingadc? general functional block diagram the total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an oversampled a/d converter. the reference volt age can be selected on two different channels. two offset compensation amplifiers allow for a wide offset compensation range. the programmable gain and offset give the ability to zoom in on a small portion of the reference voltage defined input range. 17.3 register map there are eight registers in t he acquisition chain (ac), namely regacoutlsb , regacoutmsb , regaccfg0 , regaccfg1 , regaccfg2 , regaccfg3 , regaccfg4 and regaccfg5 . table 17-2 to table 17-9 show the mapping of control bits and functionality of these registers while table 17-1 gives an overview of these eight. the register map only gives a short description of the different configuration bits. more detailed information is found in subsequent sections.
17-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver register name regacoutlsb regacoutmsb regaccfg0 regaccfg1 regaccfg2 regaccfg3 regaccfg4 regaccfg5 table 17-1: ac registers pos. regacoutlsb rw reset description 7:0 out[7:0] r 00000000 nresetglobal lsb of the output code table 17-2: regacoutlsb pos. regacoutmsb rw reset description 7:0 out[15:8] r 00000000 nresetglobal msb of the output code table 17-3: regacoutmsb pos. regaccfg0 rw reset description 7 start w r0 0 nresetglobal starts a conversion 6:5 set_nelconv[1:0] r w 01 nresetglobal sets the number of elementary conversions 4:2 set_osr[2:0] r w 010 nresetglobal sets the oversampling rate of an elementary conversion 1 cont r w 0 nresetglobal continuous conversion mode 0 reserved r w 0 nresetglobal table 17-4: regaccfg0 pos. regaccfg1 rw reset description 7:6 ib_amp_adc[1:0] r w 11 nr esetglobal bias current sele ction of the adc converter 5:4 ib_amp_pga[1:0] r w 11 nresetglobal bi as current selection of the pga stages 3:0 enable[3:0] r w 0000 nresetblobal enables the different pga stages and the adc table 17-5: regaccfg1 pos. regaccfg2 rw reset description 7:6 fin[1:0] r w 00 nresetglobal sampling frequency selection 5:4 pga2_gain[1:0] r w 00 nresetglobal pga2 stage gain selection 3:0 pga2_offset[3:0] r w 0000 nresetglobal pga2 stage offset selection table 17-6: regaccfg2 pos. regaccfg3 rw reset description 7 pga1_gain r w 0 nresetglobal pga1 stage gain selection 6:0 pga3_gain[6: 0] r w 0000000 nresetglobal pga3 stage gain selection table 17-7: regaccfg3
17-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regaccfg4 rw reset description 7 reserved r 0 unused 6:0 pga3_offset[6:0] r w 0000000 nresetglobal pga3 stage offset selection table 17-8: regaccfg4 pos. regaccfg5 rw reset description 7 busy r 0 nresetglobal activity flag 6 def w r0 0 selects default configuration 5:1 amux[4:0] r w 00000 nresetglobal input channel config uration selector 0 vmux r w 0 nresetglobal reference channel selector table 17-9: regaccfg5 17.4 zoomingadc?d escription figure 17-2 gives a more detailed desc ription of the acquisition chain. 17.4.1 acquisition chain figure 17-1 shows the general block diagram of the acquisition chain (ac). a control block (not shown in figure 17-1) manages all communications with the coolrisc? microcontroller. analog inputs can be selected among eight input cha nnels, while reference input is selected between two differential channels. the core of the zooming section is made of three differential programmable amplifiers (pga). after selection of a combination of input and reference signals v in and v ref , the input voltage is modulated and amplified through stages 1 to 3. fine gain prog ramming up to 1'000v/v is possible. in addition, the last two stages provide programmable offs et. each amplifier can be bypassed if needed. the output of the pga stages is directly fed to the analog-to-digital converte r (adc), which converts the signal v in,adc into digital. like most adcs intended for instrumentation or sensing applications, the zoomingadc? is an over- sampled converter (see note 1 ). the adc is a so-called incremental converter, with bipolar operation (the adc accepts both positive and negative input vo ltages). in first approx imation, the adc output result relative to full-scale ( fs ) delivers the quantity: 2 / 2 / , ref adc in adc v v fs out ? (eq. 1) in two's complement (see sections 17.4 and 17.7 for details). the output code out adc is - fs /2 to + fs /2 for v in,adc ? - v ref /2 to + v ref /2 respectively. as will be shown in section 17.6, v in,adc is related to input voltage v in by the relationship: ref tot in tot adc in v gdoff v gd v ? ? ? = , (v) (eq. 2) where gd tot is the total pga gain, and gdoff tot is the total pga offset. 1 note: over-sampled converters are operated with a sampling frequency f s much higher than the input signal's nyquist rate (typically f s is 20-1'000 times the input signal bandwidth). the sampling fr equency to throughput ratio is large (typically 10-500). these converters include digital decimation filtering. they are mainly used for high resolution, and/or low-to-medium speed applications.
17-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pga1 pga2 pga3 adc mux register bank acquisition chain gd1 gd2 gd3 off2 off3 0 1 2 3 4 5 6 7 0 1 2 3 ac_a ac_r regacoutlsb regacoutmsb 8 8 sampling frequency f s adc busy flag default settings conversion start nbr of elementary cycles over-sampling ratio continuous vs. on-request power saving modes pga enabling regaccfg5 regaccfg4 regaccfg3 regaccfg2 regaccfg1 regaccfg0 5 2 4 7 7 inputs v in f s v ref v in,adc f s mux figure 17-2. zoomingadc? detailed functional block diagram 17.4.2 peripheral registers figure 17-2 shows a detail ed functional diagram of the zoomingadc?. in table 17-10 the configuration of the peripheral registers is detailed. the system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain ( regaccfg0 to 5 ), and two registers are used to store the output c ode of the analog-to-digital conversion ( regacoutmsb & lsb ). the register coding of the adc parameters and performance characteristics are detailed in section 17.7. table 17-10. peripheral registers to configure the acquisition chain (ac) and to store the analog-to-digital conversion (adc) result bit position register name 7 6 5 4 3 2 1 0 regacoutlsb out[7:0] regacoutmsb out[15:8] regaccfg0 default values: start 0 set_nelc[1:0] 01 set_osr[2:0] 010 cont 0 test 0 regaccfg1 default values: ib_amp_adc[1:0] 11 ib_amp_pga[1:0] 11 enable[3:0] 0001
17-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver cont? bit position register name 7 6 5 4 3 2 1 0 regaccfg2 default values: fin[1:0] 00 pga2_gain[1:0] 00 pga2_offset[3:0] 0000 regaccfg3 default values: pga1_g 0 pga3_gain[6:0] 0000000 regaccfg4 default values: 0 pga3_offset[6:0] 0000000 regaccfg5 default values: busy 0 def 0 amux[4:0] 00000 vmux 0 with: ? out : (r) digital output code of the analog-to-digit al converter. (msb = out[15] ) ? start : (w) setting this bit triggers a single conversion (after the current one is finished). this bit always reads back 0. ? set_nelc : (rw) sets the number of elementary conversions to 2 set_nelc[1:0] . to compensate for offsets, the input signal is chopped between elementary conversions (1,2,4,8). ? set_osr : (rw) sets the over-sampling rate ( osr ) of an elementary conversion to 2 (3+set_osr[2:0]) . osr = 8, 16, 32, ..., 512, 1024. ? cont : (rw) setting this bit starts a conversion. a new conversion will automatically begin as long as the bit remains at 1. ? test : bit only used for test purposes. in normal mode, th is bit is forced to 0 and cannot be overwritten. ? ib_amp_adc : (rw) sets the bias current in the adc to 0.25*(1+ ib_amp_adc[1:0] ) of the normal operation current (25, 50, 75 or 100% of nominal current) . to be used for low-power, low-speed operation. ? ib_amp_pga : (rw) sets the bias current in the pgas to 0.25*(1+ ib_amp_pga[1:0] ) of the normal operation current (25, 50, 75 or 100% of nominal curr ent). to be used for low-power, low-speed operation. ? enable : (rw) enables the adc modulator (bit 0) and the di fferent stages of the pgas (pgai by bit i=1,2,3). pga stages that are disabled are bypassed. ? fin : (rw) these bits set the sampling frequency of the ac quisition chain. expressed as a fraction of the oscillator frequency, the samp ling frequency is given as: 00 ? 1/4 f rc , 01 ? 1/8 f rc , 10 ? 1/32 f rc , 11 ? ~8khz. ? pga1_gain : (rw) sets the gain of the first stage: 0 ? 1, 1 ? 10. ? pga2_gain : (rw) sets the gain of the second stage: 00 ? 1, 01 ? 2, 10 ? 5, 11 ? 10. ? pga3_gain : (rw) sets the gain of the third stage to pga3_gain[6:0] ? 1/12. ? pga2_offset : (rw) sets the offset of the second stage betw een ?1 and +1, with increments of 0.2. the msb gives the sign (0 positive, 1 negative); amplitude is coded with the bits pga2_offset[5:0] . ? pga3_offset : (rw) sets the offset of the third stage betwe en ?5.25 and +5.25, with increments of 1/12. the msb gives the sign (0 positive, 1 negative); amplitude is coded with the bits pga3_offset[5:0] . ? busy : (r) set to 1 if a conversion is running. ? def : (w) sets all values to their defaults (pga disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and st arts a new conversion without waiting the end of the preceding one. ? amux(4:0): (rw) amux[4] sets the mode (0 ? 4 differential inputs, 1 ? 7 inputs with a(0) = common reference) amux(3) sets the sign (0 ? straight, 1 ? cross) amux[2:0] sets the channel. ? vmux : (rw) sets the differential reference channel (0 ? r(1) and r(0) , 1 ? r(3) and r(2) ). (r = read; w = write; rw = read & write)
17-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.4.3 continuous-time vs. on-request the adc can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit cont ). in "continuous-time" mode, the input signal is repeat edly converted into digital. after a conversion is finished, a new one is automatically initiated. the ne w value is then written in the result register, and the corresponding internal trigger pulse is generated . this operation is sketched in figure 17-3. the conversion time in this case is defined as t conv . internal trig ouput code regacout[15:0] t conv busy irq figure 17-3. adc "continuous-time" operation internal trig ouput code regacout[15:0] t conv request start busy irq figure 17-4. adc "on-request" operation in the "on-request" mode, the internal behavior of the converter is the same as in the "continuous- time" mode, but the conversion is initiated on user request (with the start bit). as shown in figure 17-4, the conversion time is also t conv . 17.5 input multiplexers the zoomingadc? has eight analog inputs ac_a(0) to ac_a(7) and four reference inputs ac_r(0) to ac_r(3) . let us first define the differential input voltage v in and reference voltage v ref respectively as: inn inp in v v v ? = (v) (eq. 3) and: refn refp ref v v v ? = (v) (eq. 4) as shown in table 17-11 the inputs can be configured in two ways: either as 4 differential channels ( v in1 = ac_a(1) - ac_a(0) ,..., v in4 = ac_a(7) - ac_a(6) ), or ac_a(0) can be used as a common reference, providing 7 signal paths all referenced to ac_a(0) . the control word for the analog input selection is amux[4:0] . notice that the bit amux[3] controls the sign of the input voltage.
17-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver amux[4:0] (regaccfg5[5:1]) v inp v inn amux[4:0] (regaccfg5[5:1]) v inp v inn 00x00 00x01 00x10 00x11 ac_a(1) ac_a(3) ac_a(5) ac_a(7) ac_a(0) ac_a(2) ac_a(4) ac_a(6) 01x00 01x01 01x10 01x11 ac_a(0) ac_a(2) ac_a(4) ac_a(6) ac_a(1) ac_a(3) ac_a(5) ac_a(7) 10000 10001 10010 10011 10100 10101 10110 10111 ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) ac_a(0) 11000 11001 11010 11011 11100 11101 11110 11111 ac_a(0) ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) table 17-11. analog input selection similarly, the reference voltage is chosen among two differential channels ( v ref1 = ac_r(1)- ac_r(0) or v ref2 = ac_r(3)-ac_r(2) ) as shown in table 17-12. the selection bit is vmux . the reference inputs v refp and v refn (common-mode) can be up to the power supply range. vmux (regaccfg5[0]) v refp v refn 0 ac_r(1) ac_r(0) 1 ac_r(3) ac_r(2) table 17-12. analog reference input selection 17.6 programmable gain amplifiers as seen in figure 17-1, the zooming function is implemented with three programmable gain amplifiers (pga). these are: ? pga1: coarse gain tuning ? pga2: medium gain and offset tuning ? pga3: fine gain and offset tuning all gain and offset settings are realized with ratios of capacitors. the user has control over each pga activation and gain, as well as the offset of stages 2 and 3. these functions are examined hereafter. enable[3:0] block xxx0 xxx1 adc disabled adc enabled xx0x xx1x pga1 disabled pga1 enabled x0xx x1xx pga2 disabled pga2 enabled 0xxx 1xxx pga3 disabled pga3 enabled table 17-13. adc & pga enabling
17-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pga1_gain pga1 gain gd 1 (v/v) 0 1 1 10 table 17-14. pga1 gain settings pga2_gain[1:0] pga2 gain gd 2 (v/v) 00 1 01 2 10 5 11 10 table 17-15. pga2 gain settings pga2_offset[3:0] pga2 offset gdoff 2 (v/v) 0000 0 0001 +0.2 0010 +0.4 0011 +0.6 0100 +0.8 0101 +1 1001 -0.2 1010 -0.4 1011 -0.6 1100 -0.8 1101 -1 table 17-16. pga2 offset settings pga3_gain[6:0] pga3 gain gd 3 (v/v) 0000000 0 0000001 1/12(=0.083) ... ... 0000110 6/12 ... ... 0001100 12/12 0010000 16/12 ... 0100000 32/12 ... 1000000 64/12 ... 1111111 127/12(=10.58) table 17-17. pga3 gain settings
17-10 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pga3_offset[6:0] pga3 offset gdoff 3 (v/v) 0000000 0 0000001 +1/12(=+0.083) 0000010 +2/12 ... ... 0010000 +16/12 ... ... 0100000 +32/12 ... ... 0111111 +63/12(=+5.25) 1000000 0 1000001 -1/12(=-0.083) 1000010 -2/12 ... ... 1010000 -16/12 ... ... 1100000 -32/12 ... ... 1111111 -63/12(=-5.25) table 17-18. pga3 offset settings 17.6.1 pga & adc enabling depending on the application objectives, the user may enable or bypass each pga stage. this is done using the word enable and the coding given in table 17-13. to reduce power dissipation, the adc can also be inactivated while idle. 17.6.2 pga1 the first stage can have a buffer function (unity gai n) or provide a gain of 10 (see table 17-14). the voltage v d1 at the output of pga1 is: in d v gd v ? = 1 1 (v) (eq. 5) where gd 1 is the gain of pga1 (in v/v) controlled with the bit pga1_gain . 17.6.3 pga2 the second pga has a finer gain and offset tuni ng capability, as shown in table 17-15 and table 17-16. the voltage v d2 at the output of pga2 is given by: ref d d v gdoff v gd v ? ? ? = 2 1 2 2 (v) (eq. 6) where gd 2 and gdoff 2 are respectively the gain and offset of pga2 (in v/v). these are controlled with the words pga2_gain[1:0] and pga2_offset[3:0] . 17.6.4 pga3 the finest gain and offset tuning is performed with the third and last pga stage, according to the coding of table 17-17 and table 17-18. the output of pga3 is also the input of the adc. thus, similarly to pga2, we find that the voltage entering the adc is given by:
17-11 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver ref d adc in v gdoff v gd v ? ? ? = 3 2 3 , (v) (eq. 7) where gd 3 and gdoff 3 are respectively the gain and offset of pga3 (in v/v). the control words are pga3_gain[6:0] and pga3_offset[6:0] . to remain within the signal compliance of the pga stages, the condition: dd d d v v v < 2 1 , (v) (eq. 8) must be verified. finally, combining equations eq. 5 to eq. 7 for the three pga stages, the input voltage v in,adc of the adc is related to v in by: ref tot in tot adc in v gdoff v gd v ? ? ? = , (v) (eq. 9) where the total pga gain is defined as: 1 2 3 gd gd gd gd tot ? ? = (v/v) (eq. 10) and the total pga offset is: 2 3 3 gdoff gd gdoff gdoff tot ? + = (v/v) (eq. 11) 17.7 adc characteristics the main performance characteristics of the adc (r esolution, conversion time, etc.) are determined by three programmable parameters: ? sampling frequency f s , ? over-sampling ratio osr , and ? number of elementary conversions n elconv . the setting of these parameters and the resulting performances are described hereafter. 17.7.1 conversion sequence a conversion is started each time the bit start or the bit def is set. as depicted in figure 17-5, a complete analog-to-digital conversion sequence is made of a set of n elconv elementary incremental conversions and a final quantitative step. ea ch elementary conversion is made of ( osr +1) sampling periods t s =1/ f s , i.e.: s elconv f osr t / ) 1 ( + = (s) (eq. 12) the result is the mean of the elementary conver sion results. an important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if n elconv 2). a few additional clock cycles are also required to in itiate and end the conversion properly.
17-12 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver conversion index offset t elconv = (osr+1)/f s elementary conversion 1 + elementary conversion 2 - elementary conversion n elconv - 1 + elementary conversion n elconv - init end t conv conversion result figure 17-5. analog-to-digital conversion sequence 17.7.2 sampling frequency the word fin[1:0] is used to select the sampling frequency f s (table 17-19). three sub-multiples of the internal rc-based frequency f rcext can be chosen. for fin = "11", sampling frequency is about 8khz. additional information on oscillators and their control can be found in the clock block documentation. sampling frequency f s (hz) fin[1:0] lc01/05 lc02 00 1/4 ? f rc 1/8 ? f rcext 01 1/8 ? f rc 1/16 ? f rcext 10 1/32 ? f rc 1/64 ? f rcext 11 8khz 4khz table 17-19. sampling frequency settings ( f rc = rc-based frequency) 17.7.3 over-sampling ratio the over-sampling ratio ( osr ) defines the number of integration cycles per elementary conversion. its value is set with the word set_osr[2:0] in power of 2 steps (see table 17-20) given by: 0] : set_osr[2 3 2 + = osr (-) (eq. 13) set_osr[2:0] (regaccfg0[4:2]) over-sampling ratio osr (-) 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 table 17-20. over-sampling ratio settings
17-13 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.7.4 elementary conversions as mentioned previously, the whole c onversion sequence is made of a set of n elconv elementary incremental conversions. this number is set with the word set_nelc[1:0] in binary steps (see table 17-21) given by: 0] : set_nelc[1 2 = elconv n (-) (eq. 14) set_nelc[1:0] (regaccfg0[6:5]) # of elementary conversions n elconv (-) 00 1 01 2 10 4 11 8 table 17-21. number of elementary conversion settings as already mentioned, n elconv must be equal or greater than 2 to reduce internal amplifier offsets. 17.7.5 resolution the theoretical resolution of the adc, wit hout considering thermal noise, is given by: ) ( log ) ( log 2 2 2 elconv n osr n + ? = (bits) (eq. 15) 5 7 9 11 13 15 17 000 001 010 011 100 101 110 111 set _ osr resolution - n [bits] 11 10 01 00 set _ nelc= figure 17-6. resolution vs. set_osr[2:0] and set_nelc[2:0] set_nelc set_osr [2:0] 00 01 10 11 000 6 7 8 9 001 8 9 10 11 010 10 11 12 13 011 12 13 14 15 100 14 15 16 16 101 16 16 16 16 110 16 16 16 16 111 16 16 16 16 (shaded area: resolution truncated to 16 bits due to output register size regacout[15:0] ) table 17-22. resolution vs. set_osr[2:0] and set_nelc[1:0] settings
17-14 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver using table 17-22 or the graph plotted in figure 17-6, resolution can be set between 6 and 16 bits. notice that, because of 16-bit register use for the adc output, practical resolution is limited to 16 bits , i.e. n 16. even if the resolution is truncated to 16 bit by the output register size, it may make sense to set osr and n elconv to higher values in order to reduce the influence of the thermal noise in the pga (see section 17.8.4). 17.7.6 conversion time & throughput as explained using figure 17-5, conversion time is given by: s elconv conv f osr n t / ) 1 ) 1 ( ( + + ? = (s) (eq. 16) and throughput is then simply 1/ t conv . for example, consider an ov er-sampling ratio of 256, 2 elementary conversions, and a sampling frequency of 500khz ( set_osr = "101", set_nelc = "01", f rc = 2mhz, and fin = "00"). in this case, using table 17-23, the conversion time is 515 sampling periods, or 1.03ms. this corresponds to a throughpu t of 971hz in continuous-time mode. the plot of figure 17-7 illustrates the classic trade-o ff between resolution and conversion time. set_nelc[1:0] set_osr [2:0] 00 01 10 11 000 10 19 37 73 001 18 35 69 137 010 34 67 133 265 011 66 131 261 521 100 130 259 517 1033 101 258 515 1029 2057 110 514 1027 2053 4105 111 1026 2051 4101 8201 table 17-23. normalized conversion time ( t conv ? f s ) vs. set_osr[2:0] and set_nelc[1:0] (normalized to sampling period 1/ f s ) 4.0 6.0 8.0 10.0 12.0 14.0 16.0 10.0 100.0 1000.0 10000.0 normalized conversion time - t conv *f s [-] resolution - n [bits] 00 set_nelc 01 10 11 figure 17-7. resolution vs. normalized conversion time for different set_nelc[1:0] 17.7.7 output code format the adc output code is a 16-bit word in two's co mplement format (see table 17-24). for input voltages outside the range, the output code is saturat ed to the closest full-scale value (i.e. 0x7fff or 0x8000). for resolutions smaller than 16 bits, the non- significant bits are forced to the values shown in table 17-25. the output code, expressed in lsbs, corresponds to: osr osr v v out ref adc in adc 1 2 , 16 + ? ? = (lsb) (eq.17)
17-15 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver recalling equation eq. 9, this can be rewritten as: ? ? ? ? ? ? ? ? ? ? ? ? = in ref tot tot ref in adc v v gdoff gd v v out 16 2 osr osr 1 + ? (lsb) (eq. 18) where, from eq. 10 and eq. 11, the total pga gain and offset are respectively: 1 2 3 gd gd gd gd tot ? ? = (v/v) and: 2 3 3 gdoff gd gdoff gdoff tot ? + = (v/v) adc input voltage v in,adc % of full scale (fs) output in lsbs output code in hex +2.49505v +0.5 ? fs +2 15 -1 =+32'767 7fff +2.49497v ... +2 15 -2 =+32'766 7ffe ... ... ... ... +76.145 v ... +1 0001 0v 0 0 0000 -76.145 v ... -1 ffff ... ... ... ... -2.49505v ... -2 15 -1 =-32'767 8001 -2.49513v -0.5 ? fs -2 15 =-32'768 8000 table 17-24. basic adc re lationships (example for: v ref = 5v, osr = 512, n = 16 bits) set_osr [2:0] set_nelc = 00 set_nelc = 01 set_nelc = 10 set_nelc = 11 000 1000000000 100000000 10000000 1000000 001 10000000 1000000 100000 10000 010 100000 10000 1000 100 011 1000 100 10 1 100 10 1 - - 101 - - - - 110 - - - - 111 - - - - table 17-25. last forced lsbs in conversion output registers for resolution settings smaller than 16 bits ( n < 16) ( regacoutmsb[7:0] & regacoutlsb[7:0] ) the equivalent lsb size at the input of the pga chain is: 1 2 1 + ? ? = osr osr gd v lsb tot ref n (v) (eq. 19) notice that the input voltage v in,adc of the adc must satisfy the condition:
17-16 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 1 ) ( 2 1 , + ? ? ? osr osr v v v refn refp adc in (v) (eq. 20) to remain within the adc input range. 17.7.8 power saving modes during low-speed operation, the bias current in the pgas and adc can be programmed to save power using the control words ib_amp_pga[1:0] and ib_amp_adc[1:0] (see table 17-26). if the system is idle, the pgas and adc can even be disabled, thus, reducing power consumption to its minimum. this can considerably improve battery lifetime. ib_amp_adc [1:0] ib_amp_pga [1:0] adc bias current pga bias current max. f s [khz] 00 01 10 11 x 1/4 ? i adc 1/2 ? i adc 3/4 ? i adc i adc x 62.5 125 250 500 x 00 01 10 11 x 1/4 ? i pga 1/2 ? i pga 3/4 ? i pga i pga 62.5 125 250 500 table 17-26. adc & pga power saving modes and maximum sampling frequency 17.8 specifications and measured curves this section presents measurement results for the acquisition chain. a summary table with circuit specifications and measured curves are given. 17.8.1 default settings unless otherwise specified, the meas urement conditions are the following: ? temperature t a = +25c ? v dd = +5v, gnd = 0v, v ref = +5v, v in = 0v ? rc frequency f rc = 2mhz, sampling frequency f s = 500khz ? offsets gdoff 2 = gdoff 3 = 0 ? power operation: normal ( ib_amp_adc[1:0] = ib_amp_pga[1:0] = '11') ? resolution: for n = 12 bits: osr = 32 and n elconv = 4 o for n = 16 bits: osr = 512 and n elconv = 2
17-17 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.8.2 specifications unless otherwise specified: temperature t a = +25c, v dd = +5v, gnd = 0v, v ref = +5v, v in = 0v, rc frequency f rc = 2mhz, sampling frequency f s = 500khz, overall pga gain gd tot = 1, offsets gdoff 2 = gdoff 3 = 0. power operation: normal ( ib_amp_adc[1:0] = ib_amp_pga[1:0] = '11'). for resolution n = 12 bits: osr = 32 and n elconv = 4. for resolution n = 16 bits: osr = 512 and n elconv = 2. value parameter min typ max units comments/conditions analog input characteristics differential input voltage ranges v in = (v inp - v inn ) reference voltage range v ref = (v refp ? v refn ) -2.42 -24.2 -2.42 +2.42 +24.2 +2.42 v dd v mv mv v gain = 1, osr = 32 (note 1) gain = 100, osr = 32 gain = 1000, osr = 32 programmable gain amplifiers (pga) total pga gain, gd tot pga1 gain, gd 1 pga2 gain, gd 2 pga3 gain, gd 3 gain setting precision (each stage) gain temperature dependence offset pga2 offset, gdoff 2 pga3 offset, gdoff 3 offset setting precision (pga2 or 3) offset temperature dependence input impedance pga1 pga2, pga3 output rms noise pga1 pga2 pga3 0.5 1 1 0 -3 -1 -127/12 -3 1500 150 150 0.5 5 0.5 5 205 340 365 1000 10 10 127/12 +3 +1 +127/12 +3 v/v v/v v/v v/v % ppm/c v/v v/v % ppm/c k ? k ? k ? v v v see table 17-14 see table 17-15 step=1/12 v/v, see table 17-17 step=0.2 v/v, see table 17-16 step=1/12 v/v, see table 17-18 (note 2) pga1 gain = 1 (note 3) pga1 gain = 10 (note 3) maximal gain (note 3) (note 4) (note 5) (note 6) adc static performance resolution, n no missing codes gain error offset error integral non-linearity, inl resolution n = 16 bits differential non-linearity, dnl resolution n = 16 bits power supply rejection ratio, psrr 6 0.15 1 1.0 0.5 78 72 16 bits % of fs lsb lsb lsb db db (note 7) (note 8) (note 9) n = 16 bits (note 10) (note 11) (note 12) v dd = 5v 0.3v (note 13) v dd = 3v 0.3v (note 13) dynamic performance sampling frequency, f s conversion time, t conv throughput rate (continuous mode), 1/t conv nbr of initialization cycles, n init nbr of end conversion cycles, n end pga stabilization delay 3 0 0 133 1027 3.76 0.49 osr 2 5 khz cycles/f s cycles/f s ksps ksps cycles cycles cycles n = 12 bits (note 14) n = 16 bits (note 14) n = 12 bits, f s = 500khz n = 16 bits, f s = 500khz (note 15) digital output adc output data coding binary two?s complement see table 17-24 and table 17-25
17-18 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver specifications (cont?d) value parameter min typ max units comments/conditions power supply voltage supply range, v dd analog quiescent current consumption, total (i q ) adc only pga1 pga2 pga3 analog power dissipation normal power mode 3/4 power reduction mode 1/2 power reduction mode 1/4 power reduction mode +2.4 +5 720/620 250/190 165/150 130/120 175/160 3.6/1.9 2.7/1.4 1.8/0.9 0.9/0.5 +5.5 v a a a a a mw mw mw mw only acquisition chain v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v all pgas & adc active v dd = 5v/3v (note 16) v dd = 5v/3v (note 17) v dd = 5v/3v (note 18) v dd = 5v/3v (note 19) temperature specified range operating range -40 -40 +85 +125 c c notes: (1) gain defined as overall pga gain gd tot = gd 1 ? gd 2 ? gd 3 . maximum input voltage is given by: v in,max = (v ref /2) ? (osr/osr+1). (2) offset due to tolerance on gdoff 2 or gdoff 3 setting. for small intrinsic offset, use only adc and pga1. (3) measured with block connected to inputs through am ux block. normalized input sampling frequency for input impedance is f s = 512khz. this figure must be multiplied by 2 for f s = 256khz, 4 for f s = 128khz. input impedance is proportional to 1/ f s . (4) figure independent from pga1 gain and sampling frequency f s . see model of figure 17-18(a). see equation eq. 21 to calculate equivalent input noise. (5) figure independent on pga2 gain and sampling frequency f s . see model of figure 17-18(a). see equation eq. 21 to calculate equivalent input noise. (6) figure independent on pga3 gain and sampling frequency f s . see model of figure 17-18(a) and equation eq. 21 to calculate equivalent input noise. (7) resolution is given by n = 2 ? log2( osr ) + log2( n elconv ). osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (8) if a ramp signal is applied to the input, all di gital codes appear in the resulting adc output data. (9) gain error is defined as the amount of deviation betw een the ideal (theoretical) transf er function and the measured transfer function (with the offset error removed). (see figure 17-19) (10) offset error is defined as the output code erro r for a zero volt input (ideally, output code = 0). for 1 lsb offset, n elconv must be 2. (11) inl defined as the deviation of the dc transfer curve of each individual code from the best-fit straight line. this specification holds over the full scale. (12) dnl is defined as the difference (in lsb) between the ideal (1 lsb) and measured code transitions for successive codes. (13) figures for gains = 1 to 100. psrr is defined as the amount of change in the adc output value as the power supply voltage changes. (14) conversion time is given by: t conv = ( n elconv ? ( osr + 1) + 1) / f s . osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (15) pgas are reset after eac h writing operation to registers regaccfg1-5 . the adc must be started after a pga or inputs common-mode stabilisation delay. this is done by writing bit start several cycles after pga settings modification or channel switching. delay between pga st art or input channel switching and adc start should be equivalent to osr (between 8 and 1024) number of cycles. this de lay does not apply to conversions made without the pgas. (16) nominal (maximum) bias currents in pgas and adc, i.e. ib_amp_pga[1:0] = ?11? and ib_amp_adc[1:0] = ?11?. (17) bias currents in pgas and adc set to 3/4 of nominal values, i.e. ib_amp_pga[1:0] = ?10?, ib_amp_adc[1:0] = ?10?. (18) bias currents in pgas and adc set to 1/2 of nominal values, i.e. ib_amp_pga[1:0] = ?01?, ib_amp_adc[1:0] = ?01?. (19) bias currents in pgas and adc set to 1/4 of nominal values, i.e. ib_amp_pga[1:0] = ?00?, ib_amp_adc[1:0] = ?00?.
17-19 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.8.3 linearity 17.8.3.1 integral non-linearity the integral non-linearity depends on the selected gain configuration. first of all, the non-linearity of the adc (all pga stages bypassed) is shown in figure 17-8. figure 17-8. integral non-linearity of the adc (pga disabled, reference voltage of 4.8v) the different pga stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. to obtain this, the first stage has the best noise performance and the third stage the be st linearity performance. for large input signals (small pga gains, i.e. up to about 50), the noise added by the pga is very small with respect to the input signal and the second and third stage of the pg a should be used to get the best linearity. for small input signals (large gains, i.e. above 50), the noi se level in the pga is important and the first stage of the pga should be used. the following figures give the non-linearity for different gain settings of the pga, selecting the appropriate stage to get the best noise and linearity performance. figure 17-9 shows the non-linearity when the third stage is used with a gain of 1. it is of course not very useful to use the pga with a gain of 1 unless it is used to compensate offset. by in creasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces. figure 17-10 shows the non-linearity for a gain of 2. figure 17-11 shows the non-linearity for a gain of 5. figure 17-12 shows the non-linearity for a gain of 10. by comparing these figures to figure 17-8, it can be seen that the third stage of the pga doe s not add significant integral non-linearity. figure 17-13 shows the non-linearity for a gain of 20 and figure 17-14 shows the non-linearity for a gain of 50. in both cases the pga2 is used at a gai n of 10 and the remaining gain is realized by the third stage. it can be seen again that the seco nd stage of the pga does not add significant non- linearity. for gains above 50, the first stage pga1 should be selected instead of pga2. although the non- linearity in the first stage of the pga is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity of the first stage does become negligible as is shown in figure 17-15 for a gain of 100. therefore, the first stage is preferred over the second stage since it has less noise. increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the first two stages. the signal is full sc ale at the output of stage 3 and as shown in figure 17-9 to figure 17-12, this stage has very good linearity.
17-20 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver figure 17-9. integral non-linearity of the adc and with gain of 1 (pga1 and pga2 disabled, pga3=1, reference voltage of 5v) figure 17-10. integral non-linearity of the adc and gain of 2 (pga1 and pga2 disabled, pga3=2 reference voltage of 5v) figure 17-11. integral non-linearity of the adc and gain of 5 (pga1 and pga2 disabled, pga3=5, reference voltage of 5v)
17-21 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver figure 17-12. integral non-linearity of the adc and gain of 10 (pga1 and pga2 disabled, pga3=10, reference voltage of 5v) figure 17-13. integral non-linearity of the adc and gain of 20 (pga1 and pga2=10, pga3=2, reference voltage of 5v)
17-22 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver figure 17-14. integral non-linearity of the adc and gain of 50 (pga1 disabled, pga2=10, pga3=5, reference voltage of 5v) figure 17-15. integral non-linearity of the adc and gain of 100 (pga1=10 and pga3=10, pga2 disabled, reference voltage of 5v) 17.8.3.2 differential non-linearity the differential non-linearity is generated by the ad c. the pga does not add differential non-linearity. figure 17-16 shows the differential non-linearity.
17-23 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver figure 17-16. differential non-linearity of the adc converter. 17.8.4 noise ideally, a constant input voltage v in should result in a constant output code. however, because of circuit noise, the output code may vary for a fixed input voltage. thus, a statistical analysis on the output code of 1200 conversions for a constant inpu t voltage was performed to derive the equivalent noise levels of pga1, pga2, and pga3. the extracted rms output noise of pga1, 2, and 3 are given in table 17-27: standard output deviation and output rms noise voltage. figure 17-17 shows the distribution for the adc alone (pga1, 2, and 3 bypassed). quantitative noise is dominant in this case, and, thus, the adc thermal noise is below 16 bits. the simple noise model of figure 17-18(a) is used to estimate the equivalent input referred rms noise v n,in of the acquisition chain in the model of figur e 17-18(b). this is given by the relationship: ) ( )) /( ( )) /( ( ) / ( 2 3 2 1 3 2 2 1 2 2 1 1 2 , elconv n n n in n n osr gd gd gd v gd gd v gd v v ? ? ? + ? + = (v 2 rms) (eq. 21) where v n1 , v n2 , and v n3 are the output rms noise figures of table 17-27, gd 1 , gd 2 , and gd 3 are the pga gains of stages 1 to 3 respectively. as shown in this equation, noise can be reduced by increasing osr and n elconv (increases the adc averaging effect, but reduces noise). parameter pga1 pga2 pga3 standard deviation at adc output (lsb) 0.85 1.4 1.5 output rms noise ( v) 1 205 (v n1 ) 340 (v n2 ) 365 (v n3 ) note: see noise model of figure 17-18 and equation eq. 21. table 17-27. pga noise measurements ( n = 16 bits, osr = 512, n elconv = 2, v ref = 5v)
17-24 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 0 20 40 60 80 -5 -4 -3 -2 -1 0 1 2 3 4 5 output code deviation from mean value [lsb] occurences [% of total samples] figure 17-17. adc noise (pga1, 2 & 3 bypassed, osr=512,n elconv =2) pga1 pga2 pga3 adc gd1 gd2 gd3 v n1 f s v n2 v n3 (a) pga1 pga2 pga3 adc gd1 gd2 gd3 v n,in f s (b) figure 17-18. (a) simple noise model for pgas and adc and (b) total input referred noise as an example, consider the system where: gd 2 = 10 ( gd 1 = 1; pga3 bypassed), osr = 512, n elconv = 2, v ref = 5v. in this case, the noise contribution v n1 of pga1 is dominant over that of pga2. using equation eq. 21, we get: v n,in = 6.4 v (rms) at the input of the acquisition chain, or, equivalently, 0.85 lsb at the output of the adc. co nsidering a 0.2v (rms) maximum signal amplitude, the signal-to-noise ratio is 90db. implementing a software filter can also reduce noise. by taking an average on a number of subsequent measurements, the appa rent noise is reduced by the square root of the number of measurement used to make the average. 17.8.5 gain error and offset error gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation eq. 18) and the measured transfer func tion (with the offset error removed). the actual gain of the different stages can vary re lating to the fabrication to lerances of the different elements. although these tolerances are specified to a maximum of 3%, most of the time they will be around 0.5%. moreover, the tolerances between t he different stages are not correlated and the probability of getting the maximal error in the same di rection in all stages is very low. finally, the software can calibrate these gain errors at the same ti me as the gain errors of the sensor for instance. figure 17-19 shows gain error drift vs. temperature fo r different pga gains. the curves are expressed in % of full-scale range (fsr) normalized to 25c.
17-25 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver offset error is defined as the output code error for a zero volt input (ideally, output code = 0). the offset of the adc and the pga1 st age are completely suppressed if n elconv > 1. the measured offset drift vs. temperature curves fo r different pga gains are depicted in figure 17-20. the output offset error, expressed in lsb for 16-bit se tting, is normalized to 25 c. notice that if the adc is used alone, the output offset error is below 1 lsb and has no drift. normalized to 25c -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 -50 -25 0 25 50 75 100 temperature [c] gain error [% of fsr] 1 5 20 100 figure 17-19. gain error vs. temperature for different pga gains normalized to 25c -40 -20 0 20 40 60 80 100 -50 -25 0 25 50 75 100 temperature [c] output offset error [lsb] 1 5 20 100 figure 17-20. offset error vs. temperature for different pga gains 17.8.6 power consumption figure 17-21 plots the variation of quiescent current consumption with supply voltage v dd , as well as the distribution between the 3 pga stages and the a dc (see table 17-28). as shown in figure 17-22, if lower sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the pgas and the adc with registers ib_amp_pga [1:0] and ib_amp_adc [1:0] . (in figure 17-22, ib_amp_pga/adc[1:0] = '11', '10', '00' for f s = 500, 250, 62.5khz respectively.) quiescent current consumption vs. temperature is depicted in figure 17-23, showing a relative increase of nearly 40% between - 45 and +85c. figure 17-24 shows t he variation of quiescent current consumption for different frequency settings of the internal rc osc illator. it can be seen that the quiescent current varies by about 20% between 100khz and 2mhz.
17-26 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 100 200 300 400 500 600 700 800 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage - v dda [v] quiescent current - i q [ a] no pgas, adc only pga1 + adc pga1 & 2 + adc pga1, 2 & 3 + adc figure 17-21. quiescent current consumption vs. supply voltage 100 200 300 400 500 600 700 800 2.53.03.54.04.55.05.5 supply voltage - v dda [v] quiescent current - i q [ a] 500khz sampling frequency f s : 250khz 62.5khz figure 17-22. quiescent current consumption vs. supply voltage for different sampling frequencies 500 550 600 650 700 750 800 850 900 -50 -25 0 25 50 75 100 125 temperature [c] quiescent current - i q [ a] -25 -20 -15 -10 -5 0 5 10 15 20 -50-25 0 255075100125 temperature [c] relative quiescent current change i q / i q,25c [%] (a) (b) figure 17-23. (a) absolute and (b) relative change inquiescent current consumption vs. temperature
17-27 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver supply adc pga1 pga2 pga3 total unit v dd = 5v 250 165 130 175 720 a v dd = 3v 190 150 120 160 620 a table 17-28. typical quiescent current distributions in acquisition chain (n = 16 bits, f s = 500khz) -20 -15 -10 -5 0 5 10 15 0 500 1000 1500 2000 2500 3000 3500 frequency - f rc [khz] relative quiescent current change ? i q / i q,2m hz [%] 500 550 600 650 700 750 800 850 0 500 1000 1500 2000 2500 3000 3500 frequency - f rc [khz] quiescent current - i q [ a] (a) (b) figure 17-24. (a) absolute and (b) relative change in quiescent curent consumption vs. rc oscillator frequency (all pgas active, v dd = 5v) 17.8.7 power supply rejection ratio figure 17-25 shows power supply rejection ratio (p srr) at a 3v and a 5v supply voltage, and for various pga gains. psrr is defined as the ratio (in db ) of voltage supply change (in v) to the change in the converter output (in v). psrr depends on both pga gain and supply voltage v dd . 60 65 70 75 80 85 90 95 100 105 1 5 10 20 100 pga gain [v/v] psrr [db] vdd=3v vdd=5v figure 17-25. power supply rejection ratio (psrr) supply gain = 1 gain =5 gain = 10 gain = 20 gain =100 unit v dd = 5v 79 78 100 99 97 db v dd = 3v 72 79 90 90 86 db table 17-29. psrr (n = 16 bits, v in = v ref = 2.5v, f s = 500khz)
17-28 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.9 application hints 17.9.1 input impedance the pgas of the acquisition chain employ switched -capacitor techniques. for this reason, while a conversion is done, the input impedance on the sele cted channel of the pgas is inversely proportional to the sampling frequency f s and to stage gain as given in equation 22. gain f hz z s in ? ? ? 9 10 768 (eq. 22) the input impedance observed is the input impedance of the first pga stage that is enabled or the input impedance of the adc if all three stages are disabled. pga1 (with a gain of 10), pga2 (with a gain of 10) and pga3 (with a gain of 10) each have a minimum input impedance of 150k ? at f s = 512khz (see specification table). larger input impedance can be obtained by reducing the gain and/or by reduci ng the sampling frequency. therefore, with a gain of 1 and a sampling frequency of 100khz, z in > 7.6m ? . the input impedance on channels that ar e not selected is very high (>100m ? ). 17.9.2 pga settling or input channel modifications pgas are reset after each writing operation to registers regaccfg1-5 . similarly, input channels are switched after modifications of amux[4:0] or vmux . to ensure precise conversion, the adc must be started after a pga or inputs common-mode stabiliz ation delay. this is done by writing bit start several cycles after modification of pga settings or channel switching. delay between pga start or input channel switching and adc start should be equivalent to osr (between 8 and 1024) number of cycles. this delay does not apply to conversions made without the pgas. if the adc is not settled within the specified per iod, there is probably an input impedance problem (see previous section). 17.9.3 pga gain & offset, linearity and noise hereafter are a few design guidelines that sh ould be taken into account when using the zoomingadc?: 1) keep in mind that increasing the overa ll pga gain, or "zooming" coefficient, improves linearity but degrades noise performance. 2) use the minimum number of pga stages nece ssary to produce the desired gain ("zooming") and offset. bypass unnecessary pgas. 3) for high gains (>50), use pga stage 1. for low gains (<50) use stages 2 and 3. 4) for the lowest noise, set the highest possible gain on the first (front) pga stage used in the chain. for example, in an application where a ga in of 20 is needed, set the gain of pga2 to 10, set the gain of pga3 to 2. 4) for highest linearity and lowest noise perf ormance, bypass all pgas and use the adc alone (applications where no "zooming" is needed); i.e. set enable[3:0] = '0001'. 5) for low-noise applications where power consum ption is not a primary concern, maintain the largest bias currents in the pgas and in the adc; i.e. set ib_amp_pga[1:0] = ib_amp_adc[1:0] = '11'. 6) for lowest output offset error at the output of the a dc, bypass pga2 and pga3. indeed, pga2 and pga3 typically introduce an offset of about 5 to 10 lsb (16 bit) at their output. note, however, that the adc output offset is easily calibrated out by software.
17-29 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 17.9.4 frequency response the incremental adc is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. the main function of the di gital filter is to remove the quantitative noise introduced by the modulator. as shown in figure 17- 26, this filter determines the frequency response of the transfer function between the output of the adc and the analog input v in . notice that the frequency axes are normalized to one elementary conversion period osr / f s . the plots of figure 17-26 also show that the frequency response ch anges with the number of elementary conversions n elconv performed. in particular, notches appear for n elconv 2. these notches occur at: elconv s notch n osr f i i f ? ? = ) ( (hz) for ) 1 ( ,..., 2 , 1 ? = elconv n i (eq. 23) and are repeated every f s / osr . information on the location of these notches is pa rticularly useful when sp ecific frequencies must be filtered out by the acquisition syst em. for example, consider a 5hz- bandwidth, 16-bit sensing system where 50hz line rejection is needed. using the a bove equation and the plots below, we set the 4th notch for n elconv = 4 to 50hz, i.e. 1.25 ? f s / osr = 50hz. the sampling frequency is then calculated as f s = 20.48khz for osr = 512. notice that this choice yiel ds also good attenuation of 50hz harmonics. 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 1 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 2 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 4 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 8 figure 17-26. frequency response: normalized magnitude vs. frequency for different n elconv 17.9.5 power reduction the zoominadc? is particularly well suited fo r low-power applications . when very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: 1) operate the acquisition chain with a reduced supply voltage v dd . 2) disable the pgas which are not used during analog-to-digital conversion with enable[3:0] . 3) disable all pgas and the adc when the syst em is idle and no conversion is performed.
17-30 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 4) use lower bias currents in the pgas and the adc using the control words ib_amp_pga[1:0] and ib_amp_adc[1:0] . (this reduces the maximum sampling frequency according to table 17-26.) 5) reduce internal rc oscillator frequency and/or sampling frequency. finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed.
18-1 voltage multiplier ? 1.0 ? 28 nove mbre 2000 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 18. voltage multiplier 18.1 features 18-2 18.2 overview 18-2 18.3 control part registers 18-2
18-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 18.1 features ? generates a voltage that is higher or equal to the supply voltage, but at maximum 4.8 v ? can be easily enabled or disabled 18.2 overview en_vmult vmult (analog) vmult (capacitor only required when enabled) switched analog (other blocks) regs prescaler vmult_dl ck_vmult switch power figure 17-1 : structure of the vmult peripheral the vmult block generates a voltage (called ?vmult?) that is higher or equal to the supply voltage. this output voltage is intended for use in analog switch drivers, for example in the adc and pga block. ? in normal use its value is 4.8 v, this voltage is available on the pad vmult. ? when the main voltage is below 2.6 v, vmult is twice the main voltage minus 0.4 v. ? when the main voltage is above 4.8 v, vmult remains 4.8 v but the internal voltage intended for the analog switch drivers equal the main voltage. the voltage multiplier should be on (bit enable in regvmultcfg0 ) when using switched analog blocks, like adc, dac or analog properties of port b when vbat is below 3v. the source clock of vmult is selected from fin[1:0] in regvmultcfg0 . it is strongly recommended to use the same fin bit code as in the adc. the external capacitor on the pin vmult has to be c onnected if the block is en abled. the size of the capacitor has to be 2nf 50%. 18.3 control part registers there is only one register in the vmult. table 18-1 describes the bits in the register. pos. regvmultcfg0 rw reset function 2 enable rw 0 enable of the vmult ?1? : enabled ?0? : disabled 1-0 fin rw 0 system clock division factor ?00? : 1/2, ?01? : 1/4, ?10? : 1/16, ?11? : 1/64 table 18-1. regvmultcfg0
19-1 lcd driver ? 1.5 ? 18 mars 2002 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19. lcd driver 19.1 f eatures ............................................................................................................................. 19 -2 19.2 o verview ............................................................................................................................ 19- 2 19.3 r egister map ...................................................................................................................... 19-3 19.4 b asic lcd capabilities ....................................................................................................... 19- 6 19.4.1 direct drive mode ....................................................................................................... ........ 19-7 19.4.2 1:2 mult iplex scheme .................................................................................................... ...... 19-9 19.4.3 1:3 mult iplex scheme .................................................................................................... .... 19-11 19.4.4 1:4 mult iplex scheme .................................................................................................... .... 19-13 19.5 a dvanced lcd features .................................................................................................. 19-15 19.5.1 register usage .......................................................................................................... ........ 19-15 19.5.2 sleep mode or blinking mode ........................................................................................... 19 -15 19.5.3 lcd frame freque ncy selection......................................................................................... 19 -16 19.5.4 voltage generation ...................................................................................................... ...... 19-17 19.6 p arallel i/o port capabilities ......................................................................................... 19-21 19.6.1 parallel po rt function .................................................................................................. ....... 19-21 19.6.2 parallel port voltage................................................................................................... ........ 19-22 19.7 partial lcd driver / partial parallel i/o port .............................................................. 19-24 19.7.1 single low impedance voltage for v3 of lcd and di gital i/o ............................................ 19-24 19.7.2 different voltage for v3 of lcd and digi tal i/o.................................................................. 19-26 19.8 s pecifications .................................................................................................................. 19-27 19.8.1 pad_lcd_io used in lcd mode.......................................................................................... 19- 27 19.8.2 pad_lcd_io used in digital i/o mode.................................................................................. 19- 27 19.8.3 voltage reference ....................................................................................................... ....... 19-28 19.8.4 lcd mult iplier/divider .................................................................................................. ...... 19-28
19-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.1 features ? supports direct drive for 32 segments. ? supports multiplexed drive for up to 120 segments ? multiplex 1/2, 1/3 and 1/4. ? possibility to use pads as an input/output port or as lcd driver pin. ? multiple frame frequencies. ? sleep mode. ? on chip low-power voltage generation. ? lcd driver voltage is independent from the circuit supply voltage. ? parallel io with voltage different from the circuit supply voltage. 19.2 overview lcd periph display memory 16x8 bits ts segments waveform generator i/o p o r t lcd pads lcd control an d mo de register vg en control register vg enpads coms waveform generator v3 v2 v1 i/o port control reg isters figure 19-1: general structure the lcd driver generates all waveforms to drive the display. the user has only to set a 0 (segment off) or a 1 (segment on) in the bit location corr esponding to the segment. the lcd driver supports the wave form generation for different multiplexing scheme s: direct drive (no multiplexing), multiplexing by 2, by 3 and by 4. the frame frequency is softw are programmable. low power on-chip voltage generation is provided for each of the different mu ltiplexing schemes. the lcd driver voltage is completely independent from the circuit supply volta ge: the lcd driver voltage can be below or above
19-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the circuit supply voltage. all or part of the driver can be configured as a general-purpose parallel io- port. when used as a parallel port, it can be connected to circuits with a different supply voltage. section 19.4 describes the basic functions of t he lcd driver using the on-chip voltage generator. section 19.5 describes more advanced the features of the lcd driver and especially different ways of generating the voltage for the lcd. section 19.6 describes how to use the peripheral as a general- purpose parallel io-port. section 19.7 shows how to partition when used as a partial lcd driver and partial io port. finally, the electrical specificat ions of the driver are given in section 19.8. 19.3 register map there are thirty-six registers in the lcd driver, namely regvgencfg0 , reglcdon , reglcdse , reglcdclkframe , reglcddatan (0 n 15), regplcdinn (0 n 3), regplcdoutn (0 n 3), regplcddirn (0 n 3) and regplcdpullupn (0 n 3). table 19-2 to table 19-11 show the mapping of control bits and functionality of these registers while table 19-1 gives the default address of these thirty-six registers. register name vgen registers regvgencfg0 control registers reglcdon reglcdse reglcdclkframe lcd registers reglcddata0 reglcddata1 reglcddata2 reglcddata3 reglcddata4 reglcddata5 reglcddata6 reglcddata7 reglcddata8 reglcddata9 reglcddata10 reglcddata11 reglcddata12 reglcddata13 reglcddata14 reglcddata15 port registers regplcdout0 regplcdout1 regplcdout2 regplcdout3 regplcddir0 regplcddir1 regplcddir2 regplcddir3 regplcdpull0 regplcdpull1 regplcdpull2 regplcdpull3 regplcdin0 regplcdin1 regplcdin2 regplcdin3 table 19-1: lcd registers default addresses
19-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regvgencfg0 rw reset function 7-6 -- r 00 unused 5-4 vgenclksel r w 10 nresetglobal voltage generator frequency selection. 00 ? 256 hz 01 ? 512 hz 10 ? 1 khz 11 ? 2 khz 3 vgenoff r w 1 nresetglobal volt age generator disable signal. 0 ? enabled 1 ? disabled 2 vgenmode r w 0 nresetglobal mode selection. 0 ? 1/3 bias 1 ? 1/2 bias 1 vgenstdb r w 0 nresetglobal stand-by mode 0 vgenrefen r w 0 nresetglobal inter nal 1.2v voltage reference enable. 0 ? disabled 1 ? enabled table 19-2: regvgencfg0 pos. reglcdon rw reset function 7-3 - 00000 2 lcdsleep r w 1 nresetglobal 1 = stop operating 0 = continue operating 1-0 lcdmux r w 00 nresetglobal 00 = direct drive 01 = 1:2 mux drive 10 = 1:3 mux drive 11 = 1:4 mux drive table 19-3: reglcdon pos. reglcdse rw reset function 7 lcdse3 r w 1 nresetglobal 1 = pins pad_lcd_io(0-3) have lcd drive function 0 = pins pad_lcd_io(0-3) have digital function 6 lcdse7 r w 1 nresetglobal 1 = pins pad_lcd_io(4-7) have lcd drive function 0 = pins pad_lcd_io(4-7) have digital function 5 lcdse11 r w 1 nresetglobal 1 = pins pad_lcd_io(8-11) have lcd drive function 0 = pins pad_lcd_io(8-11) have digital function 4 lcdse15 r w 1 nresetglobal 1 = pins pad_lcd_io(12-15) have lcd drive function 0 = pins pad_lcd_io(12-15)have digital function 3 lcdse19 r w 1 nresetglobal 1 = pins pad_lcd_io(16-19) have lcd drive function 0 = pins pad_lcd_io(16-19) have digital function 2 lcdse23 r w 1 nresetglobal 1 = pins pad_lcd_io(20-23) have lcd drive function 0 = pins pad_lcd_io(20-23) have digital function 1 lcdse27 r w 1 nresetglobal 1 = pins pad_lcd_io(24-27) have lcd drive function 0 = pins pad_lcd_io(24-27) have digital function 0 lcdse31 r w 1 nresetglobal 1 = pins pad_lcd_io(28-31) have lcd drive function 0 = pins pad_lcd_io(28-31) have digital function table 19-4: reglcdse
19-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. reglcdclkframe rw reset function 7-5 lcddivfreq r w 000 nresetglobal 000 = lcdfreq 001 = lcdfreq / 2 010 = lcdfreq / 3 011 = lcdfreq / 4 100 = lcdfreq / 5 101 = lcdfreq / 6 110 = lcdfreq / 7 111 = lcdfreq / 8 4-2 reserved - 000 1-0 lcdfreq r w 00 nresetglobal 00 = 512 hz 01 = 1024 hz 10 = 2048 hz 11 = 4096 hz table 19-5: reglcdclkframe pos. reglcddatan rw reset description map pin 7 lcddatan[7] rw 0 nresetpconf segment[3] value in 1:4 mux 6 lcddatan[6] rw 0 nresetpconf segment[2] value in 1:3 mux 5 lcddatan[5] rw 0 nresetpconf segment[1] value in 1:2 mux 4 lcddatan[4] rw 0 nresetpconf segment[0] value in dd pad_lcd_io[2n+1] 3 lcddatan[3] rw 0 nresetpconf segment[3] value in 1:4 mux 2 lcddatan[2] rw 0 nresetpconf segment[2] value in 1:3 mux 1 lcddatan[1] rw 0 nresetpconf segment[1] value in 1:2 mux 0 lcddatan[0] rw 0 nresetpconf segment[0] value in dd pad_lcd_io[2n] table 19-6 : reglcddatan with 0 n 14 pos. reglcddata15 rw reset description map pin 7 lcddata15[7] rw 0 nresetpconf -- 6 lcddata15[6] rw 0 nresetpconf -- 5 lcddata15[5] rw 0 nresetpc onf segment[1] value in 1:2 mux 4 lcddata15[4] rw 0 nreset pconf segment[0] value in dd pad_lcd_io[31] 3 lcddata15[3] rw 0 nresetpconf -- 2 lcddata15[2] rw 0 nresetpc onf segment[2] value in 1:3 mux 1 lcddata15[1] rw 0 nresetpc onf segment[1] value in 1:2 mux 0 lcddata15[0] rw 0 nreset pconf segment[0] value in dd pad_lcd_io[30] table 19-7 : reglcddata15 pos. regplcdinn rw reset description 7 plcdinn[7] r x pad_lcd_io[8n+7] input value 6 plcdinn[6] r x pad_lcd_io[8n+6] input value 5 plcdinn[5] r x pad_lcd_io[8n+5] input value 4 plcdinn[4] r x pad_lcd_io[8n+4] input value 3 plcdinn[3] r x pad_lcd_io[8n+3] input value 2 plcdinn[2] r x pad_lcd_io[8n+2] input value 1 plcdinn[1] r x pad_lcd_io[8n+1] input value 0 plcdinn[0] r x pad_lcd_io[8n+0] input value table 19-8 : regplcdinn with 0 n 3
19-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regplcdoutn rw reset description 7 plcdoun[7] r w 0 nresetpconf pad_lcd_io[8n+7] output value 6 plcdoutn[6] r w 0 nresetpconf pad_lcd_io[8n+6] output value 5 plcdoutn[5] r w 0 nresetpconf pad_lcd_io[8n+5] output value 4 plcdoutn[4] r w 0 nresetpconf pad_lcd_io[8n+4] output value 3 plcdoutn[3] r w 0 nresetpconf pad_lcd_io[8n+3] output value 2 plcdoutn[2] r w 0 nresetpconf pad_lcd_io[8n+2] output value 1 plcdoutn[1] r w 0 nresetpconf pad_lcd_io[8n+1] output value 0 plcdoutn[0] r w 0 nresetpconf pad_lcd_io[8n+0] output value table 19-9 : regplcdoutn with 0 n 3 pos. regplcddirn rw reset description 7 plcddirn[7] r w 0 nresetpconf pad_lcd_io[8n+7] direction (0=input) 6 plcddirn[6] r w 0 nresetpconf pad_lcd_io[8n+6] direction (0=input) 5 plcddirn[5] r w 0 nresetpconf pad_lcd_io[8n+5] direction (0=input) 4 plcddirn[4] r w 0 nresetpconf pad_lcd_io[8n+4] direction (0=input) 3 plcddirn[3] r w 0 nresetpconf pad_lcd_io[8n+3] direction (0=input) 2 plcddirn[2] r w 0 nresetpconf pad_lcd_io[8n+2] direction (0=input) 1 plcddirn[1] r w 0 nresetpconf pad_lcd_io[8n+1] direction (0=input) 0 plcddirn[0] r w 0 nresetpconf pad_lcd_io[8n+0] direction (0=input) table 19-10: regplcddirn with 0 n 3 pos. regplcdpullupn rw reset description 7 plcdpullupn[7] r w 0 nresetpconf pullup for pad_lcd_io[8n+7] (1=active) 6 plcdpullupn[6] r w 0 nresetpconf pullup for pad_lcd_io[8n+6] (1=active) 5 plcdpullupn[5] r w 0 nresetpconf pullup for pad_lcd_io[8n+5] (1=active) 4 plcdpullupn[4] r w 0 nresetpconf pullup for pad_lcd_io[8n+4] (1=active) 3 plcdpullupn[3] r w 0 nresetpconf pullup for pad_lcd_io[8n+3] (1=active) 2 plcdpullupn[2] r w 0 nresetpconf pullup for pad_lcd_io[8n+2] (1=active) 1 plcdpullupn[1] r w 0 nresetpconf pullup for pad_lcd_io[8n+1] (1=active) 0 plcdpullupn[0] r w 0 nresetpconf pullup for pad_lcd_io[8n+0] (1=active) table 19-11: regplcdpullupn with 0 n 3 19.4 basic lcd capabilities this section shows how to use the lcd driver. fo r each multiplexing configuration it gives a basic example explaining how to set-up the driver, the ge nerated waveforms, how to connect the display and how to use the on-chip voltage generator. other connection schemes and more advanced control functions will be given in the next section. the lcd module generates the timing control to drive a static or multiplexed lcd panel, with support for up to 32 segment lines multiplexed with up to four common lines. the table below summarises the multiplexing scheme for lcd operation. multiplex scheme max #segments direct drive (dd) 32 1:2 32 x 2 1:3 31 x 3 1:4 30 x 4 table 19-12: multiplexing scheme
19-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.4.1 direct drive mode with direct drive mode, each pad_lcd_io pin drives o ne segment of the display. in this mode, up to 32 segments of the display can be connected direct ly to the pad_lcd_io[31:0] pins. the common (or backplane) node is to be connected to pad_lcd_com[0]. this connection is shown in figure 19-2. pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr1 pad_lcd_vr2 1.2v voltage reference vgen pad_vgen_vb pad_lcd_io[31:0] pad_lcd_com1 pad_lcd_com0 lcd display segments co m0 c lcd3 lcd2 lcd1 c c c pad_vgen_v3 aux figure 19-2: lcd with direct drive and on-chip voltage generation. lots of different configurations for the voltage generation can be used. figure 19-2 shows the connections and external elements that are required if the display is to be driven from v3=3.6v independently from the circuit supply voltage. othe r possible configurations are given in section 19.5.4. the recommended value for the external elements is 470nf (see also section 19.5.4.1). to operate the driver in this configuration, the registers should be loaded with the values in table 19-13. register contents[7:0] regvgencfg0 xx110001 reglcdon xxxxx000 reglcdse 11111111 reglcdclkframe 100xxx00 table 19-13. register contents for direct drive example
19-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_lcd_com0 - pad_lcd_io[0] (off) v0 v3 pad_lcd_com0 pad_lcd_io[1] pad_lcd_io[0] v0 v3 v0 v3 pad_lcd_com0 - pad_lcd_io[1] (on) v0 -v3 v0 v3 figure 19-3 : direct drive mode waveforms the voltage generator has to be configured for the use of the internal reference ( vgenrefen =1 in regvgencfg0 ). the generator has to run ( vgenoff =0 and vgenstdb =0 in regvgencfg0 ). it has to multiply by 3 ( vgenmode =0 in regvgencfg0) and the generator output impedance is set to minimum ( vgenclksel =11 in regvgencfg0) . the lcd driver is set to direct drive ( lcdmux =00 in reglcdon ) and the waveform generator is enabled ( lcdsleep =0 in reglcdon ). all pads are set into the lcd driver mode by setting all bits of register reglcdse to 1. to select a frame rate of about 50hz, set the bits lcdfreq =00 and lcddivfreq =100 in reglcdclkframe . note that the precision of the frame frequency depends on the selected clock source (see clock block documentation). the 32 segments are on or off depending on the bits set in the registers reglcddatan . only the bits 0 and 4 of these registers are used in direct drive. all other bits are don?t ca re. figure 19-3 shows the generated waveforms for two segments. segment0 is off ( lcddata0[0] =0 in reglcddata0 ) and segment1 is on ( lcddata0[4] =1 in reglcddata0 ). the figure shows on the left side the waveforms on the circuit pins, in the middle the segment status and on the right the voltage on the segment (difference between the pad_lcd_io pin and pad_lcd_com0 pin).
19-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.4.2 1:2 multiplex scheme with the 1:2 multiplex scheme, each pad_lcd_io pin drives two segments of t he display. the segments of the display are connected to the pad_lcd_io[31:0] pins. the common (or backplane) nodes are to be connected to pad_lcd_com0 and pad_lcd_com1. this connection is shown in figure 19-4. pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr1 pad_lcd_vr2 1.2v voltage reference vgen pad_vgen_vb pad_lcd_io[31:0] pad_lcd_com1 pad_lcd_com0 lcd display segments co m0 c lcd2 lcd1 c c pad_vgen_v3 aux co m1 figure 19-4. lcd with 1:2 multiplexing a nd on-chip 1/2 bias voltage generation. lots of different configurations for the voltage generation can be used. figure 19-4 shows the connections and external elements that are required if the display is to be driven from v2=1.2v and v3=2.4v independently from the circuit supply voltage. other possible configurations are given in section 19.5.4. recommended values for the external capacitors are 470nf. to operate the driver in this configuration, the registers should be loaded with the values in table 19-14. register contents[7:0] regvgencfg0 xx110101 reglcdon xxxxx001 reglcdse 11111111 reglcdclkframe 100xxx01 table 19-14. register contents for 1:2 mux example the voltage generator has to be configured for the use of the internal reference ( vgenrefen =1 in regvgencfg0 ). the generator has to run ( vgenoff =0 and vgenstdb =0 in regvgencfg0 ). it has to be in 1/2 bias ( vgenmode =1 in regvgencfg0) and the generator output impedance is set to minimum ( vgenclksel =11 in regvgencfg0) .
19-10 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_lcd_com0 pad_lcd_com1 pad_lcd_io[0] pad_lcd_io[1] v0 v2 v3 v0 v2 v3 v0 v2 v3 v0 v2 v3 pad_lcd_com0 - pad_lcd_io[0] (on) pad_lcd_com1 - pad_lcd_io[1] (off) -v3 v0 v3 v2 -v2 -v3 v0 v3 v2 -v2 figure 19-5. 1:2 mux mode waveforms the lcd driver is set to 1:2 multiplexing ( lcdmux =01 in reglcdon ) and the waveform generator is enabled ( lcdsleep =0 in reglcdon ). all pads are set into the lcd driver mode by setting all bits of register reglcdse to 1. to select a frame rate of about 50hz, set the bits lcdfreq =01 and lcddivfreq =100 in reglcdclkframe . note that the precision of the frame frequency depends on the selected clock source (see clock block documentation). the 64 segments are on or off depending on the bits set in the registers reglcddatan . only the bits 0,1 and 4,5 of these registers are used in 1: 2 multiplexing. figure 19-5 shows the generated waveforms for four segments. segments connected to pad_lcd_io[0] are on ( lcddata0[1:0] =11 in reglcddata0 ) and segments connected to pad_lcd_io[1] are off ( lcddata0[5:4] =00 in reglcddata0 ). the figure shows on the left side the waveforms on the circuit pins, in the middle the segment status and on the right the voltage on th e segment (difference between the segment pin pad_lcd_io and common signal pad_lcd_com0 or pad_lcd_com1).
19-11 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.4.3 1:3 multiplex scheme with 1:3 multiplexing, each pad_lcd_io pin can drive th ree segments of the display. in this mode, up to 93 segments of the display can be driven by the pad_lcd_io[30:0] pins. the common nodes are to be connected to the pad_lcd_com0, pad_lcd_com1 and pad_lcd_io[31]. these connections are shown in figure 19-6. pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr1 pad_lcd_vr2 1.2v voltage reference vgen pad_vgen_vb pad_lcd_io[30:0] pad_lcd_com1 pad_lcd_com0 lcd display segments co m0 c lcd3 lcd2 lcd1 c c c pad_vgen_v3 aux pad_lcd_io[31] co m1 co m2 figure 19-6: lcd with 1:3 multiplexing and on-chip 1/3 bias voltage generation. lots of different configurations for the voltage generation can be used. figure 19-6 shows the connections and external elements that are requi red if the display is to be driven from 3.6v independently from the circuit supply voltage. othe r possible configurations are given in section 19.5.4. the recommended value for the external capacitors is 470nf. to operate the driver in this configuration, the registers should be loaded with the values in table 19-15. register contents[7:0] regvgencfg0 xx110001 reglcdon xxxxx010 reglcdse 11111111 reglcdclkframe 110xxx10 table 19-15. register contents for 1:3 mux example
19-12 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_lcd_com0 pad_lcd_io[31] pad_lcd_com1 pad_lcd_io[0] pad_lcd_io[1] pad_lcd_io[2] pad_lcd_com0 - pad_lcd_io[0] (on) pad_lcd_com1 - pad_lcd_io[1] (off) v0 v2 v3 v1 v0 v2 v3 v1 v0 v2 v3 v1 v0 v2 v3 v1 v0 v2 v3 v1 v0 v2 v3 v1 -v2 -v1 -v3 v0 v2 v3 v1 -v2 -v1 -v3 pad_lcd_io[31] - pad_lcd_io[2] (on) v0 v2 v3 v1 -v2 -v1 -v3 v0 v2 v3 v1 figure 19-7. 1:3 mux mode waveforms the voltage generator has to be configured for the use of the internal reference ( vgenrefen =1 in regvgencfg0 ). the generator has to run ( vgenoff =0 and vgenstdb =0 in regvgencfg0 ). it has to generate 1/3 bias ( vgenmode =0 in regvgencfg0) and the generator output impedance is set to minimum ( vgenclksel =11 in regvgencfg0) . the lcd driver is set to 1:3 multiplexing ( lcdmux =10 in reglcdon ) and the waveform generator is enabled ( lcdsleep =0 in reglcdon ). all pads are set into the lcd driver mode by setting all bits of register reglcdse to 1. to select a frame rate of about 50hz, set the bits lcdfreq =10 and lcddivfreq =110 in reglcdclkframe . note that the precision of the frame frequency depends on the selected clock source (see clock block documentation). the 93 segments are on or off depending on the bits set in the registers reglcddatan . only the bits 0,1,2 and 4,5,6 of these r egisters are used in 1:3 multiplexing. the bits 3 and 7 are not important. figure 19-7 shows the generated waveforms fo r nine segments. the segments connected to
19-13 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_lcd_io[0] are all on ( lcddata0[2:0] =111 in reglcddata0 ), the segments connected to pad_lcd_io[1] are all off ( lcddata0[6:4] =000 in reglcddata0 ) and the segments connected to pad_lcd_io[2] are partially on, partially off ( lcddata1[2:0] =101 in reglcddata1 ). the figure shows on the left side the waveforms on the circuit pins, in the middle the segment status and on the right the voltage on some segments (difference between the segment pin pad_lcd_io and common signals: pad_lcd_com0, pad_lcd_com1 or pad_lcd_io[31]). 19.4.4 1:4 multiplex scheme pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr1 pad_lcd_vr2 1.2v voltage reference vgen pad_vgen_vb pad_lcd_io[29:0] pad_lcd_io[31] pad_lcd_com1 pad_lcd_com0 lcd display pad_lcd_io[30] segments co m3 co m2 co m1 co m0 c lcd3 lcd2 lcd1 c c c pad_vgen_v3 aux figure 19-8: lcd with 1:4 multiplexing a nd on-chip 1/3 bias voltage generation. with 1:4 multiplexing, each pin pad_lcd_io can drive four segments of the display. in this mode, up to 120 segments of the display can be driven by the pa d_lcd_io[29:0] pins. the common nodes are to be connected to the pad_lcd_com0, pad_lcd_com1, pad_lcd_io[31] and pad_lcd_io[30]. these connections are shown in figure 19-8. lots of different configurations for the voltage generation can be used. figure 19-8 shows the connections and external elements that are required if the display is to be driven from v3=3.6v, v2=2.4v and v1=1.2v independently from the circuit su pply voltage. other possible configurations are given in section 19.5.4. the recommended val ue for the external capacitors is 470nf.
19-14 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver p ad_ lcd_com 0 - p ad_lcd_ io [0] (on ) p ad_ lcd_com 1 - p ad_lcd_ io [1] (off) -v2 -v1 -v3 p ad_ lcd_ io [3 0] - pad_ lcd_ io [2 ] (on) v0 v2 v3 p ad_ lcd_com 1 v1 v0 v2 v3 p ad_ lcd_com 0 v1 v0 v2 v3 p ad_ lcd_ io [3 0] v1 v0 v2 v3 p ad_ lcd_ io [3 1] v1 v0 v2 v3 p ad_ lcd_ io [0 ] v1 v0 v2 v3 p ad_ lcd_ io [1 ] v1 v0 v2 v3 p ad_ lcd_ io [2 ] v1 frame frequency v0 v2 v3 v1 -v2 -v1 -v3 v0 v2 v3 v1 v2 v3 v1 v0 -v2 -v1 -v3 figure 19-9. 1:4 mux mode waveforms to operate the driver in this configuration, the registers should be loaded with the values in table 19-16. the voltage generator has to be configured for the use of the internal reference ( vgenrefen =1 in regvgencfg0 ). the generator has to run ( vgenoff =0 and vgenstdb =0 in regvgencfg0 ). it has to generate 1/3 bias ( vgenmode =0 in regvgencfg0) and the generator output impedance is set to minimum ( vgenclksel =11 in regvgencfg0) . register contents[7:0] regvgencfg0 xx110001 reglcdon xxxxx011 reglcdse 11111111 reglcdclkframe 100xxx10 table 19-16. register contents for 1:4 mux example
19-15 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the lcd driver is set to 1:4 multiplexing ( lcdmux =11 in reglcdon ) and the waveform generator is enabled ( lcdsleep =0 in reglcdon ). all pads are set into the lcd driver mode by setting all bits of register reglcdse to 1. to select a frame rate of about 50hz, set the bits lcdfreq =10 and lcddivfreq =100 in reglcdclkframe . note that the precision of the frame frequency depends on the selected clock source (see clock block documentation). the 120 segments are on or off depending on the bits set in the registers reglcddatan . all bits of these registers are used in 1:4 multiplexing. figu re 19-9 shows the generated waveforms for twelve segments. the segments connected to pad_lcd_io[0] are all on ( lcddata0[3:0] =1111 in reglcddata0 ), the segments connected to pad_lcd_io[1] are all off ( lcddata0[7:4] =0000 in reglcddata0 ) and the segments connected to pad_lcd_i o[2] are partially on, partially off ( lcddata1[2:0] =1101 in reglcddata1 ). the figure shows on the left side the waveforms on the circuit pins, in the middle the segment status and on the right the voltage on some segments (difference between the pad_lcd_io pin and common signal: pad_lcd_com0, pad_lcd_com1, pad_lcd_io[31] or pad_lcd_io[30]). 19.5 advanced lcd features 19.5.1 register usage to set the peripheral in lcd mode, all bits in reglcdse have to be set to 1. the status of the segments has to be written to the registers reglcddatan (with 0 19-16 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver v0 v2 v3 v1 v0 v2 v3 v1 lcdsl eep frame 2 frame 0 frame 1 sleep figure 19-10. sleep mode synchronisation 19.5.3 lcd frame frequency selection 512 hz 1024 hz 2048 hz 4096 hz 00 01 10 11 lc df r eq( 1: 0) 3-bit programmable divider lcddivfreq(2:0) internal state generator frame rate f requency lcdmux(1:0) figure 19-11: frame rate generation the lcd driver frame frequency depends on three pa rameters: the selected clock source frequency, the selected division factor and the multiplexing scheme . as shown in figure 19-11, four different clock source frequencies can be selected by setting the bits lcdfreq in reglcdclkframe . this frequency is further divided by a factor between 1 and 8 depending on the bits lcddivfreq in reglcdclkframe . it further depends on the selected multiplexing scheme (bits lcdmux in reglcdon ). the selections are defined in table 19-18 to table 19-20. the frame rate fr is then given by: mux div f fr lcd ? ? = 2 finally, table 19-21 shows the minimal and maximal frame rate for each multiplexing. the source frequency should be chosen as low as possible to reduce the power consumption. note that the precision of the frame rate depends on the precis ion of the selected clock source (see clock block documentation).
19-17 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver lcdfreq lcd f [hz] 00 512 01 1048 10 2048 11 4096 table 19-18. lcd driver source frequency selection lcddivfreq div 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 table 19-19. lcd driver frequency division lcdmux multiplexing scheme mux 00 direct drive 1 01 1:2 2 10 1:3 3 11 1:4 4 table 19-20. lcd multiplexing lcdmux lcdfreq lcddivfreq fr [hz] 00 00 111 32 00 11 000 2048 01 00 111 16 01 11 000 1024 10 00 111 10.6 10 11 000 682.7 11 00 111 8 11 11 000 512 table 19-21. minimal and maximal frame rate 19.5.4 voltage generation the different voltages used in the lcd driver can be generated in several ways. depending on the selected multiplexing scheme, the lcd display driver needs 2, 3 or 4 different voltages. the reference voltage can be derived from an internal 1.2v band gap reference or from an externally supplied voltage. the circuit also contains a volt age multiplier/divider that can be configured to generate a 1/2 bias or a 1/3 bias. this multiplier/ divider needs external capacitors. instead of the internal multiplier/divider, an external resistive ladde r can be used. the use of the internal circuitry will in most applications give the lowest power solution. the voltages v0, v1 and v2 are connected internal ly in the circuit. the voltage v3 is not connected internally but externally by short-circuiting t he pins pad_lcd_vr1 and pad_lcd_vr2 to pad_vgen_v3. the voltages used in the lcd driver for the differ ent multiplexing schemes are given in table 19-22.
19-18 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver multpilexing v0 v1 v2 v3 direct drive used - - used 1:2 used - used used 1:3 used used used used 1:4 used used used used table 19-22. v0, v1, v2, v3 usage in the lcd driver 19.5.4.1 generating lcd voltage with the internal multiplier/divider. to generate lcd voltage with the internal multipli er/divider, some external capacitors have to be connected to the circuit. the value of the capacitor aux c can be calculated depending on the output impedance that is required on the v3 voltage: 3 6 outv vgen aux z f c ? ? with vgen f the operating frequency of the multiplier/divider (set by the bits vgenclksel in regvgencfg0 , see table 19-23) and 3 outv z the required output impedance of v3. the equation is valid for aux c <5 f. note that the operating frequency depends on the selected clock source (see clock block documen- tation). for a capacitor aux c of 470nf and a frequency of 1024hz (default value), an output impedance of 12k ? is obtained. the capacitors c lcd1 , c lcd2 and c lcd3 can be chosen equal to aux c . vgenclksel vgen f (hz) 00 256 01 512 10 1024 11 2048 table 19-23. multplier/divider operating frequency to enable the voltage multiplier/divider, the bits vgenoff and vgenstdb in regvgencfg0 are set to 0. the difference between the two bits is that vgenoff stops the generator and forces the nodes pad_vgen_v1, pad_vgen_v2, pad_vgen_ v3, pad_vgen_va and pad_vgen_vb to predefined values and therefor discharges the capacitors c lcd1 , c lcd2 and c lcd3 . the bit vgenstdb only stops the operating clock without changing the voltage on c lcd1 , c lcd2 and c lcd3 . the capacitors will be discharged by leakage and by the switchi ng of the lcd if the bit lcdsleep is not set. the multiplier/divider can generate 1/2 bias ( vgenmode =1 in regvgencfg0 ) or 1/3 bias ( vgenmode =0 in regvgencfg0 ). finally, the multiplier/divider can use the internal 1.2v bandgap reference ( vgenrefen =1 in regvgencfg0 ) or an external reference ( vgenrefen =0 in regvgencfg0 ). the internal voltage reference can not be used in case the circuit voltage supply is below 1.5v. figure 19-12 shows the external connections to be ma de in 1/3 bias mode. part (a) of the figure shows the use of the internal voltage reference. in this case, v1=1.2v, v2=2.4v and v3=3.6v. part (b)
19-19 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver of the figure shows the use of an external voltage reference. the ex ternal reference can be connected to one of the pins pad_vgen_v1, pad_vgen_v2, pad_vgen_v3. table 19-24 shows the voltage generated on v1, v2, v3 depending on the connection of the external reference voltage vext. the external voltage may or may not be identical to the circuit supply voltage vbat. the voltage on v3 should not exceed 5.5v. the voltage on pad_vgen_v1 should not exceed vbat. vgenoff = 0 vgenrefen = 1 vgenmode = 0 vgen aux (a) pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_v gen_v b pad_v gen_v a 1.2v v oltage ref erence c lcd3 c lcd2 c lcd1 c lcd driv er vgenoff = 0 vgenrefen = 0 vgenmode = 0 voltage vext pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_v gen_v b pad_v gen_v a 1.2v v oltage ref erence vgen c lcd3 c lcd2 c lcd1 c aux lcd driv er (b) figure 19-12: generation of lcd voltage with external capacitors for 1/3 bias mode. vext connection v1 (v) v2 (v) v3 (v) pad_vgen_v1 vext 2 ? vext 3 ? vext pad_vgen_v2 (1/2) ? vext vext (3/2) ? vext pad_vgen_v3 (1/3) ? vext (2/3) ? vext vext table 19-24. v1, v2 and v3 as a function of the external reference connection in 1/3 bias mode figure 19-13 shows the external connections to be made in 1/2 bias mode. part (a) of the figure shows the use of the internal voltage reference. in this case, v1=v2=1.2v and v3=2.4v. part (b) of the figure shows the use of an external voltage reference. th e external reference can be connected to one of the pins pad_vgen_v1 or pad_vgen_v3. table 19 -25 shows the voltage generated on v1 and v3 depending on the connection of the external refer ence voltage vext. the external voltage may or may not be identical to the circuit supply voltage vbat. the voltage on v3 should not exceed 5.5v. vext connection v1 (v) v3 (v) pad_vgen_v1 vext 2 ? vext pad_vgen_v3 (1/2) ? vext vext table 19-25. v1 and v3 as a function of the external reference connection in 1/2 bias mode
19-20 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver vgenoff = 0 vgenrefen = 1 vgenmode = 1 pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_v gen_v b pad_gen_v a 1.2v v oltage ref erence vgen c lcd3 c lcd1 c aux lcd driv er (a) vgenoff = 0 vgenrefen = 0 vgenmode = 1 voltage vext pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_v gen_v b pad_v gen_v a 1.2v v oltage ref erence vgen c lcd3 c lcd1 c aux lcd driv er (b) figure 19-13: generation of lcd voltage with external capacitors for 1/2 bias mode. finally, in direct drive, there is no need for in termediate voltages. the configurations of figure 19-12(a) or figure 19-13(a) can still be used (depending on the required voltage: 2.4v or 3.6v) but the configurations in figure 19-12(b) or figure 19-13( b) can be replaced by the simple schematic of figure 19-14. the external voltage vext may or may not be identical to the circuit supply voltage vbat. vgenoff = 1 vgenrefen = 0 pad_gen_v 3 pad_gen_v 2 pad_v gen_v 1 pad_gen_v b pad_gen_v a 1.2v voltage reference vgen lcd driver voltage vext figure 19-14. generation of lcd voltage for direct drive using external voltage. 19.5.4.2 generating lcd voltages wi th an external resistor ladder to generate the lcd voltages with an external r-lad der (figure 19-15), the internal voltage reference and multiplier/divider block are not used ( vgenoff =1 and vgenrefen =0 in regvgencfg0 ). all other bits in the register regvgencfg0 are unused. all resistor values are equal and sufficiently sma ll in order to have small lcd voltage impedance. for direct drive, no resistors are requi red as shown in figure 19-14. the voltage vext can be connected to the circuit supply voltage vbat or any other external voltage.
19-21 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver vgenoff = 1 vgenrefen = 0 pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_gen_v b pad_v gen_v a 1.2v voltage reference vgen lcd driver r 3 r 2 r 1 vgenoff = 1 vgenrefen = 0 1.2v voltage reference vgen lcd driver (b) r 3 r 1 (a) vext vext pad_gen_v b pad_v gen_v 3 pad_v gen_v 2 pad_v gen_v 1 pad_v gen_v a figure 19-15. generation of lcd voltages with external resistors ladder in 1/3 (a) and 1/2 (b) bias mode. 19.6 parallel i/o port capabilities 19.6.1 parallel port function all pins pad_lcd_io[31:0] can be used as a general in put/output digital port. the peripheral is set to this mode by writing all bits of the register reglcdse to ?0?. figure 19-16 shows the structure for one pin and the registers used in this mode. since the perip heral has 32 pins, 4 of each of the registers in figure 19-16 exist. they are labelled with the suffix 0 to 3. the mapping of the register bits to the i/o pins is given in table 19-26. as an example, the bit plcdpullup2[6] in regplcdpullup2 controls the pull up resistor of the pin pad_lcd_io[22]. suffix of the register 0 n 3 bit in the register 0 n 7 pin n n pad_lcd_io[8n+n] table 19-26. register bit to pin mapping the direction of each pin pad_lcd_i o[31:0] (input or output) can be individually set by using the regplcddirn registers. if plcddirn[n] = 1, the output buffer of t he corresponding pad_lcd_io[8n+n] is enabled. output mode: the data to be output is stored in regplcdoutn . in output mode, the pull- up resistors should be switched off by writing ?0? to the registers regplcdpullupn . if not, current will fl ow through the pull-up resistors when the output is forced to ?0?.
19-22 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver regplcdpullup regplcddir r regplcdout regplcdin port figure 19-16. structure of the lcd driver used as parallel port input mode: the status of the pins pad_lcd_io is available in regplcdinn (read only). reading is always direct, there is no digital debounce function. in case of noisy input signals, a software debouncer or an external filter must be realised. the pull-up resistors are individually controllable fo r each pin by setting the corresponding bit in the registers regplcdpulln (1=active, 0=inactive). 19.6.2 parallel port voltage when the peripheral is used as a parallel port, the internal voltage generator is not required ( vgenoff =1 and vgenrefen =0 in regvgencfg0 ). for normal operation as a standard parallel port, the circuit is connected as shown in figure 19-17. in this case, the logical ?1? corresponds to the voltage vbat. the parallel port can also be driven from another voltage than vbat. this allows the circuit to be interfaced to other circuits that have a different supply voltage domain vdd1 that can be either lower or higher than vbat without adding any ex tra hardware as shown in figure 19-18. the parallel port can be split in several voltage dom ains. the pins pad_lcd_io[31:12] are supplied from the pad_vgen_v3 pin. the pins pad_l cd_io[11:4] are supplied from t he pin pad_lcd_vr1 and the pins pad_lcd_io[3:0] are supplied from the pin pad_lcd_vr2. each of these can be supplied with a different voltage as shown in figure 19-19. as an example, vbat could be supplied at 2.7v, vdd1 at 2.2v, vdd2 at 3.3v and vdd3 at 5v. the only limitati on is that vdd1>vreg, vdd2>vreg, vdd3>vreg.
19-23 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_vgen_v3 pad_vgen_vb 1.2v voltage reference vgen vgenoff = 1 vgenrefen = 0 v1 v2 v3 pad_vgen_v2 pad_vgen_v1 pad_vgen_va vbat pad_lcd_vr2 pad_lcd_vr1 vss figure 19-17. parallel port voltage connection vgenoff = 1 vdd1 domain i/o[31:0] vdd1 vss pad_vgen_v3 pad_vgen_vb 1.2v voltage reference vgen vgenrefen = 0 pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr2 pad_lcd_vr1 vss vbat vdd1 pad_lcd_io[31:0] figure 19-18. parallel port voltage connection with i/o levelshifting
19-24 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_io[31:12] pad_vgen_v3 vdd3 i/os v dd3 pad_lcd_io[3:0] pad_lcd_vr2 pad_lcd_io[11:4] pad_lcd_vr1 vdd2 vdd1 i/os i/os pad_vgen_vb vbat domain vss v dd2 v dd1 vbat vdd1 domain vdd2 domain vdd3 domain vgen_off = 1 vgen_ref_en = 0 1.2v voltage reference vgen vbat figure 19-19. multi voltage parallel port interface 19.7 partial lcd driver / partial parallel i/o port it is perfectly possible to combine different modes de scribed in the previous sections on different pins. using the bits lcdse in the register reglcdse , the pins pad_lcd_io[31:0] can be set as parallel port or as lcd drivers. each bit sets the mode for 4 pins (see table 19-4). when combining the lcd and digital port functions, care has to be taken with the voltage generation. the logical ?1? of the digital i/o is driven from the v3 rail and needs to be low impedance. the v3 of the pins used for digital i/o can not be supplied by the on-circuit voltage multiplier. the next sections show different possibilities. 19.7.1 single low impedance voltage for v3 of lcd and digital i/o if v3 in the lcd driver is supplied from a low imp edance voltage supply (as e.g. in figure 19-12(b) or figure 19-13(b) with connection of vext to pad_vge n_v3, or in figure 19-14 and figure 19-15), the partitioning of the pins pad_lcd_io[31:0] between th e lcd driver function and the digital parallel port function can be chosen freely by setting the bits lcdse . vext may be equal to the circuit supply voltage vbat but this is not required. the digita l i/o pins use the voltages v0=vss and v3=vext for the logical ?0? and logical ?1? respectively.
19-25 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pad_vgen_v2 pad_vgen_v1 pad_vgen_va pad_lcd_vr1 pad_lcd_vr2 1.2v voltage reference vgen pad_vgen_vb pad_lcd_io[15:0] pad_lcd_io[31:24] pad_lcd_io[23:16] pad_lcd_com1 pad_lcd_com0 segments[7:0] co m1 co m0 c lcd3 lcd1 c c pad_vgen_v3 aux lcd display vbat vdd externa l circuit vss io_1[15:0] io_2[7:0] vss figure 19-20: sharing lcd (1:2 mux) and digital i/o (low impedance v3) figure 19-20 and table 19-27 show a possible example fo r such a configuration. in this case, the lcd driver voltage v3=vbat and v1=vbat/2 (1/2 bias mode, vgenmode =1, vgenrefen =0 and vgenoff =0 in regvgencfg0 ). the lcd is in 1:2 multplexing ( lcdmux =01 in reglcdon ) and lcdse19 = lcdse23 =1 while all other bits in reglcdse are 0. register contents[7:0] regvgencfg0 xx110100 reglcdon xxxxx001 reglcdse 11110011 table 19-27. register contents for configuration of figure 19-20.
19-26 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.7.2 different voltages for v3 of lcd and digital i/o when configured as a digital i/o, the logical ?1? on the pins pad_lcd_io[31:0] is identical to v3. for a part of the pad_lcd_io[31:0] pins, the v3 connection is not made inside the circuit but has to be done externally by connecting the pins pad_vgen_v3, p ad_lcd_vr1 and pad_lcd_vr2 together. this feature allows for the use of different voltages on v3 for the lcd display and for i/o parallel pins. table 19-28 shows the partitioning of the pins. the voltages that can be applied on pad_vgen_v3, pad_lcd_vr1, pad_lcd_vr2 and vbat are completely independent from each other. pin v3 connection pad_lcd_com0 pad_lcd_com1 pad_lcd_io[31:12] pad_vgen_v3 pad_lcd_io[11:4] pad_lcd_vr1 pad_lcd_io[3:0] pad_lcd_vr2 table 19-28. v3 connection of the different pad_lcd_io pins pad_lcd_io[29:12] pad_lcd_io[31] pad_lcd_com1 pad_lcd_com0 lcd display pad_lcd_io[30] segments[17:0] co m3 co m2 co m1 co m0 pad_vgen_v2 pad_vgen_v1 pad_vgen_va 1.2v voltage reference vgen pad_vgen_vb c lcd3 lcd2 lcd1 c c c pad_vgen_v3 aux vss pad_lcd_vr1 pad_lcd_io[11:4] vdd io[7:0] pad_lcd_vr2 pad_lcd_io[3:0] vdd io[3:0] vbat vdd1 vdd2 vdd1 voltage domain vdd2 voltage domain vbat vss vss ex t er na l circuit ex t er na l circuit figure 19-21. sharing lcd driver (1:4 mux) and digital i/o with v3 logic ?1?
19-27 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver as can be seen from table 19-28, the voltage v3 on the pins pad_lcd_io[31:12] can not be dissociated from the voltage v3 on the pins pad_lcd_com0, pad_lcd_com1 and the internal voltage multiplier/divider. it means that, if v3 is not a lo w impedance external voltage as in the previous section, they can be used for the lc d driver only and not for digital i/o. figure 19-21 and table 19-29 show an example. in th is case, the pins pad_lcd_io[29:12] are used to drive a display with 1:4 multiplexing ( lcdse15 = lcdse19 = lcdse23 = lcd27 = lcd31 =1 in reglcdse and lcdmux =11 in reglcdon ). in 1:4 multiplexing, the lines pad_lcd_io[31:30] are used for com2 and com3. the voltage v3 for the display is generated by the internal voltage multiplier/divider using the internal reference ( vgenoff =0, vgenrefen =1, vgenmode =0 in regvgencfg0 ). the segment status is set by using the reglcddatan registers with 6 n 15. writing in the registers with 0 n 5 will have no effect. the pins pad_lcd_io[11:0] are used as digital i/o ( lcdse3 = lcdse7 = lcdse11 =0 in reglcdse ). the control of the digital i/o is done using the registers regplcdinn , regplcdoutn , regplcddirn and regplcdpullupn with 0 n 1. writing in the registers with 2 n 3 will have no effect. the pins pad_lcd_io[11:4] and pad_lcd_io[3:0] can further be split into two different voltage domains. the voltage domains vdd1, vdd2, v3 a nd vbat are independent. the only limitation is that vdd1>vreg and vdd2>vreg. in the example v3=3.6v, vbat could be at 2.7v, vdd1 at 2.4v and vdd2 at 5v. register contents[7:0] regvgencfg0 xx110001 reglcdon xxxxx011 reglcdse 00011111 table 19-29. register contents for configuration of figure 19-21. 19.8 specifications 19.8.1 pad_lcd_io used in lcd mode specification min typ max unit description comments v1 1.1 vbat v v2, v3 1.1 5.5 v t rise-fall 25 s rise/fall time (lcd mode) (1) (2) (3) (1) rise or fall time from 10% to 90% of the output signal (2) cload=5000pf (3) v1=v2/2=v3/3=1.1v (1/3 bias) or v1=v2=v3/2=1.1v (1/2 bias) 19.8.2 pad_lcd_io used in digital i/o mode specification min typ max unit description comments pad_lcd_vr1 vreg 5.5 v pad supply voltage pad_lcd_vr2 vreg 5.5 v pad supply voltage pad_vgen_v3 vreg 5.5 v pad supply voltage r _pullud 35 100 k ? pull up/down resistance t rise-fall 1 s rise/fall time (1) (2) i od 8 ma output current drive (3) (1) rise or fall time from 10% to 90% of the output signal (2) with cload=5nf, pad_vgen_v3=pad_lcd_vr1=pad_lcd_vr2=2.4v (3) pad_vgen_v3=pad_lcd_vr1=pad_lcd_vr2=4.5v, vo ltage on pad_lcd_io=0.4v for sink current and 4.1v for source current.
19-28 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 19.8.3 voltage reference specification min typ max unit comment vref 1.0 1.17 1.34 v @20 c, vbat>2.4v ? vref/ ? t 0.2 mv/ c power supply vbat 1.5 5.5 v i_load on v1 2 ma zout on v1 1000 ? 19.8.4 lcd multiplier/divider specification min typ max unit comments settling time to 90% 30 ms (2), (4), (5) z out,v2 on v2 3 (1) 6 (2) 25 (3) k ? (4), (5) z out,v3 on v3 7 (1) 14 (2) 60 (3) k ? (4), (5) pad_vgen_v3 5.5 v (1) f(vgen_clk) = 2 khz. (2) f(vgen_clk) = 1 khz. (3) f(vgen_clk) = 0.25 khz. (4) 1/3 bias mode. (5) with 0.47 f external capacitors.
20-1 counters/pwm 1.3 ? 14 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 20. counters/pwm 20.1 f eatures .............................................................................................................................20 -2 20.2 o verview ............................................................................................................................20- 2 20.3 r egister map ......................................................................................................................20-2 20.4 i nterrupts and events map ...............................................................................................20-4 20.5 b lock schematic ................................................................................................................20-4 20.6 g eneral counter registers operation ............................................................................20-5 20.7 c lock selection .................................................................................................................20-5 20.8 c ounter mode selection ...................................................................................................20-6 20.9 c ounter / t imer mode ........................................................................................................20- 7 20.10 pwm mode ..........................................................................................................................20-8 20.11 c apture function ............................................................................................................20-10 20.12 s pecifications ..................................................................................................................20-11
20-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 20.1 features - 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules - each with 4 possible clock sources - up/down counter modes - interrupt and event generation - capture function (internal or external source) - rising, falling or both edge of capture signal (except for xtal 32 khz, only rising edge) - pa[3:0] can be used as clock inputs (debounced or direct, frequency divided by 2 or not) - 2 x 8 bits pwm or 2 x 16 bits pwm - pwm resolution of 8, 10, 12, 14 or 16 bits - complex mode combinations are possible 20.2 overview counter a and counter b are 8-bits counters and c an be combined to form a 16-bit counter. counter c and counter d exhibit the same feature. the counters can also be used to generate two pwm outputs on pb[0] and pb[1]. in pwm mode one can generate pwm functions with 8, 10, 12, 14 or 16 bits wide counters. the counters a and b can be captured by events on an internal or an ex ternal signal. the capture can be performed on both 8-bit counters running individua lly on two different clock sources or on both counters chained to form a 16-bit counter. in any case, the same capture signal is used for both counters. when the counters a and b are not chained, they can be used in several configurations: a and b as counters, a and b as captured co unters, a as pwm and b as count er, a as pwm and b as captured counter. when the counters c and d are not chained, they can be used either both as counters or counter c as pwm and counter d as counter. 20.3 register map register name regcnta regcntb regcntc regcntd regcntctrlck regcntconfig1 regcntconfig2 regcnton table 20-1. counter registers bit regcnta rw reset function 7-0 countera r 00000000 nresetglobal 8-bits counter value 7-0 countera w 00000000 nresetglobal 8-bits comparison value table 20-2. regcnta
20-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver bit regcntb rw reset function 7-0 counterb r 00000000 nresetglobal 8-bits counter value 7-0 counterb w 00000000 nresetglobal 8-bits comparison value table 20-3. regcntb note: when writing to regcnta or regcntb , the processor writes the counter comparison values. when reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit regcntc rw reset function 7-0 counterc r 00000000 nresetglobal 8-bits counter value 7-0 counterc w 00000000 nresetglobal 8-bits comparison value table 20-4. regcntc bit regcntd rw reset function 7-0 counterd r 00000000 nresetglobal 8-bits counter value 7-0 counterd w 00000000 nresetglobal 8-bits comparison value table 20-5. regcntd note: when writing regcntc or regcntd , the processor writes the counter comparison values. when reading these locations, the processo r reads back the actual counter value. bit regcntctrlck rw reset function 7-6 cntdcksel(1:0) r/w 00 nresetgl obal counter d clock selection 5-4 cntccksel(1:0) r/w 00 nresetgl obal counter c clock selection 3-2 cntbcksel(1:0) r/w 00 nresetgl obal counter b clock selection 1-0 cntacksel(1:0) r/w 00 nresetgl obal counter a clock selection table 20-6. regcntctrlck bit regcntconfig1 rw reset function 7 cntddownup r/w 0 nresetglobal counter d up or down counting (0=down) 6 cntcdownup r/w 0 nresetglobal counter c up or down counting (0=down) 5 cntbdownup r/w 0 nresetglobal counter b up or down counting (0=down) 4 cntadownup r/w 0 nresetglobal counter a up or down counting (0=down) 3 cascadecd r/w 0 nresetglobal cascade counter c & d (1=cascade) 2 cascadeab r/w 0 nresetglobal cascade counter a & b (1=cascade) 1 cntpwm1 r/w 0 nresetglobal activate pwm1 on counter c or c+d (pb(1)) 0 cntpwm0 r/w 0 nresetglobal activate pwm0 on counter a or a+b (pb(0)) table 20-7. regcntconfig1 bit regcntconfig2 rw reset function 7-6 capsel(1:0) r/w 00 nresetglobal capture source selection 5-4 capfunc(1:0) r/w 00 nres etglobal capture function 3-2 pwm1size(1:0) r/w 00 nresetglobal pwm1 size selection 1-0 pwm0size(1:0) r/w 00 nresetglobal pwm0 size selection table 20-8. regcntconfig2
20-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver bit regcnton rw reset function 7 cntdextdiv r/w 0 nresetglobal divide pa(3) frequency by 2 (1=divide) 6 cntcextdiv r/w 0 nresetglobal divide pa(2) frequency by 2 (1=divide) 5 cntbextdiv r/w 0 nresetglobal divide pa(1) frequency by 2 (1=divide) 4 cntaextdiv r/w 0 nresetglobal divide pa(0) frequency by 2 (1=divide) 3 cntdenable r/w 0 nresetglobal enable counter d 2 cntcenable r/w 0 nresetglobal enable counter c 1 cntbenable r/w 0 nresetglobal enable counter b 0 cntaenable r/w 0 nresetglobal enable counter a table 20-9. regcnton 20.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager irqa regirqhigh(4) regevn(7) irqb regirqlow(5) regevn(3) irqc regirqhigh(3) regevn(6) irqd regirqlow(4) regevn(2) table 20-10. default interrupt and event mapping. 20.5 block schematic figure 20-1: counters/timers block schematic pb(0) capture ck16k ck1k pa(0) regcnta (write) counter a pa(2) regcntc (write) counter c regcntd (write) counter d regcntb (write) counter b pa(1) pa(3) ck128 c krcext/4 ckrcext ck1k ck32k pwm pb(1) regcnta (read) regcntb (read) regcntc (read) regcntd (read)
20-5 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 20.6 general counter registers operation counters are enabled by cntaenable , cntbenable , cntcenable , and cntdenable in regcnton . to stop the counter x, cnt x enable must be reset. to start the counter x, cnt x enable must be set. when counters are cascaded, cntaenable and cntcenable also control respectively the counters b and d. warning: there should be at leas t one cpu instruct ion between the configuration of the counters and the enabling. all counters have a corresponding 8-bit read/write register: regcnta , regcntb , regcntc , and regcntd . when read, these registers contain the coun ter value (or the captured counter value). when written, they modify the counter comparison values. it is possible to read any counter at any time, even when the counter is running. the value is guaranteed to be correct when the counter is runni ng on an internal clock source. for a correct acquisition of the counter value when running on an external clock source, use one of the three following methods: 1) for slow operating counters (t ypically at least 8 times slower than the cpu clock), oversample the counter content and perform a majority operation on the consecutive read results to select the correct actual content of the counter. 2) stop the concerned counter, perform the r ead operation and restart the counter. while stopped, the counter content is frozen and the c ounter does not take into account the clock edges delivered on the external pin. 3) use the capture mechanism. when a value is written into the counter register while the counter is in counter mode, both the comparison value is updated and the counter value is modified. in upcount mode, the register value is reset to zero. in downcount mode, the comparison value is loaded into the counter. due to the synchronization mechanism betwe en the processor clock domain and the external clock source domain, this modification of the counter value can be postponed until the counter is enabled and that it receives it?s first valid clock edge. in the pwm mode or in the capture mode, the counte r value is not modified by the write operation in the counter register. changing to the counter mode, does not update the counter value (no reset in upcount, no load in downcount mode). 20.7 clock selection the clock source for each counter can be individually selected by writing the appropriate value in the register regcntctrlck . clock source for cnt x cksel(1:0) countera counterb counterc counterd 11 ck128 10 ckrcext/4 ck1k 01 ckrcext ck32k 00 pa(0) pa(1) pa(2) pa(3) table 20-11: clock sources for counters a, b, c and d
20-6 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table 20-11 gives the correspondence between the bi nary codes used for the configuration bits cntacksel(1:0) , cntbcksel(1:0), cntccksel(1:0) or cntdcksel(1:0) and the clock source selected respectively for the counters a, b, c or d. the ckrcext clock is the rc oscilla tor or external clock. the cloc ks below 32khz can be derived from the rc oscillator, the external cl ock source or the crystal oscilla tor (see the docum entation of the clock block). a separate external clock source can be delivered on porta for each individula counter. the external clock sources can be debounced or not by properly setting the porta configuration registers. additionally, the external clock sources can be divided by two in the counter block, thus enabling higher external clock frequencies, by setting the cnt x extdiv bits in the regcnton register. switching between an internal and an external clock source can only be performed while the counter is stopped. the enabling or disabling of the exte rnal clock frequency division can only be performed while the counter using this clock is stopped, or w hen this counter is running on an internal clock source. 20.8 counter mode selection each counter can work in one of the following modes: 1) counter, downcount & upcount 2) captured counter, downcount & upcount (only counters a&b) 3) pwm, downcount & upcount 4) captured pwm, downcount and upcount the counters a and b or c and d can be cascaded or not. in cascaded mode, a and c are the lsb counters while b and d are the msb counters. table 20-12 shows the different oper ation modes of the counters a and b as a function of the mode control bits. for all counter modes, the source of t he down or upcount selection is given (either the bit cntadownup or the bit cntbdownup ). also, the mapping of the in terrupt sources irqa and irqb and the pwm output on pb(0) in these different modes is shown. cascadeab countpwm0 capfunc(1:0) counter a mode counter b mode irqa source irqb source pb(0) function 0 0 00 counter 8b downup: a counter 8b downup: b counter a counter b pb(0) 1 0 00 counter 16b ab downup: a counter ab - pb(0) 0 1 00 pwm 8b downup: a counter 8b downup: b - counter b pwm a 1 1 00 pwm 10 ? 16b ab downup a - - pwm ab 0 0 1x or x1 captured counter 8b downup: a captured counter 8b downup: b capture a capture b pb(0) 1 0 1x or x1 captured counter 16b ab downup: a capture ab capture ab pb(0) 0 1 1x or x1 captured pwm 8b downup: a captured counter 8b downup: b capture a capture b pwm a 1 1 1x or x1 captured 10 ? 16b pwm (captured value on 16b) downup: a capture ab capture ab pwm ab table 20-12: operating modes of the counters a and b
20-7 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver table 20-13 shows the different oper ation modes of the counters c and d as a function of the mode control bits. for all counter modes, the source of t he down or upcount selection is given (either the bit cntcdownup or the bit cntddownup ). the mapping of the interrupt sources irqc and irqd and the pwm output on pb(1) in these different modes is also shown. the switching between different modes must be done while the concerned counters are stopped. while switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change. cascadecd countpwm1 counter c mode counter d mode irqc source irqd source pb(1) function 0 0 counter 8b downup: c counter 8b downup: d counter c counter d pb(1) 1 0 counter 16b cd downup: c counter cd - pb(1) 0 1 pwm 8b downup: c counter 8b downup: d - counter d pwm c 1 1 pwm 10 ? 16b cd downup: c - - pwm cd table 20-13: operating modes of the counters c and d 20.9 counter / timer mode the counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock periods applied on the counter clock input. each counter can be set individually either in upcount mode by setting cnt x downup in the register regcntconfig1 or in downcount mode by resetting this bit. counters a and b can be cascaded to behave as a 16 bit counter by setting cascadeab in the regcntconfig1 register. counters c and d can be cascaded by setting cascadecd . when cascaded, the up/down count modes of the counters b and d are defined respectively by the up/down count modes set for the counters a and c. when in upcount mode, the counter will start increment ing from zero up to the target value which has been written in the corresponding regcnt x register(s). when the count er content is equal to the target value, an interrupt is generated at the next counter clock pulse and the counter is loaded again with the zero value (figure 20-2). when in downcount mode, the counter will start de crementing from the initial load value which has been written in the corresponding regcnt x register(s) down to the zero value. once the counter content is equal to zero, an interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value (figure 20-2). be careful to select the counter mode (no capture, not pwm, specify cascaded or not and up or down counting mode) before writing any target or load value to the regcnt x register(s). this ensures that the counter will start from the corre ct initial value. when counters are cascaded, both counter registers must be written to ensure that both cascaded counte rs will start from the correct initial values. the stopping and consecutive starti ng of a counter in counter mode without a target or load value write operation in between can generate an interr upt if this counter has been stopped at the zero value (downcount) or at it?s target value (upcount). th is interrupt is additional to the interrupt which has already been generated when the counter reached the zero or the target value. due to the synchronization between the cpu clock and the counter clock source, it may take up to 1 cpu clock cycle before the config uration changes written in the regcntconfig x or regcnt x registers are becoming effective. in order to get correct operation of the counters, there should be at
20-8 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver least 1 software instruction between the modification of regcntconfig x or regcnt x and the enabling of the counters. figure 20-2. up and down count interrupt generation. 20.10 pwm mode the counters can generate pwm signals (pulse wi dth modulation) on the portb outputs pb(0) and pb(1). the pwm mode is selected by setting cntpwm1 and cntpwm0 in the regcntconfig1 register. see table 20-12 and table 20-13 for an exact description of how the setting of cntpwm1 and cntpwm0 affects the operating mode of the counters a, b, c and d according to the other configuration settings. when cntpwm0 is enabled, the pwma or pwmab output va lue overrides the value set in bit 0 of regpbout in the port b peripheral. when cntpwm1 is enabled, the pwmc or pwmcd output value overrides the value set in bit 1 of regpbout . the corresponding ports (0 and/or 1) of port b must be set in digital mode and as output and either open drain or not and pull up or not through a proper setting of the control registers of the port b. counters in pwm mode count down or up, according to the cnt x downup bit setting. no interrupts and events are generated by the counters that are in pwm mode. counters do count circularly: they restart at zero or at the maximal value (eithe r 0xff when not cascaded or 0xffff when cascaded) when respectively an overflow or an under flow condition occurs in the counting. d own coun ti ng clock counter x regcntx _ r xx 321032103210 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable up coun ti ng clock counter x regcntx _ r xx0 12301230123 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable
20-9 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the internal pwm signals are low as long as the counter contents are higher than the pwm code values written in the regcnt x registers. they are high when th e counter contents are smaller or equal to these pwm code values. in order to have glitch free outputs, the pwm outputs on pb(0) and pb(1) are sampled versions of these internal pwm signals, therefore delayed by one counter clock cycle. the pwm resolution is always 8 bits when the counters used for the pwm signal generation are not cascaded. pwm0size(1:0) and pwm1size(1:0) in the regcntconfig2 register are used to set the pwm resolution for the counters a and b or c and d respectively when they are in cascaded mode. the different possible resolutions in cascaded mode are shown in table 20-14. choosing a 16 bit pwm code which is higher than the maximum value t hat can be represented by the number of bits chosen for the resolution results in a pwm output which is always tied to 1. pwmxsize(1:0) resolution 11 16 bits 10 14 bits 01 12 bits 00 10 bits table 20-14: resolution selection in cascaded pwm mode small pwm code large pwm code t per t hlarge t llarge t hsmall t lsmall figure 20-3: pwm modulation examples the period of the pwm signal is given by the formula: ckcnt resolution f tper 2 = the duty cycle ratio dcr of the pwm signal is defined as: tper th dcr = dcr can be selected between resolution 2 100 % and 100 %. dcr in % in function of the regcntx content(s) is given by the relation: () ? ? ? ? ? ? + = 100 , 2 regcntx 1 100 resolution min dcr
20-10 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 20.11 capture function the 16-bit capture register is provided to fa cilitate frequency measurement s. it provides a safe reading mechanism for the counters a and b when t hey are running. when the capture function is active, the processor does not read anymore the c ounters a and b directly, but instead reads shadow registers located in the capture block. an interru pt is generated after a capture condition has been met when the shadow register content is updated. the ca pture condition is user defined by selecting either internal capture signal sources derived from the pr escaler or from the external pa(2) or pa(3) ports. both counters use the same capture condition. when the capture function is active, the a and b coun ters can either upcount or downcount. they do not count circularly: they restart at zero or at the maximal value (either 0xff when not cascaded or 0xffff when cascaded) when respectively an overflow or an underflow condition occurs in the counting. the capture function is also active on the counters when used to generate pwm signals. capfunc(1:0) in register regcntconfig2 determines if the capture function is enabled or not and selects which edges of the capture signal source ar e valid for the capture operation. the source of the capture signal can be selected by setting capsel(1:0) in the regcntconfig2 register. for all sources, rising, falling or both edge sensitivity can be select ed. table 20-15 shows the capture condition as a function of the setting of these configuration bits. capsel(1:0) selected capture signal capfunc selected condition capture condition 11 1 k 00 01 10 11 capture disabled rising edge falling edge both edges - 1 k rising edge 1 k falling edge 2 k 10 16 k 00 01 10 11 capture disabled rising edge falling edge both edges - 16 k rising edge 16 k falling edge 32 k 01 pa3 00 01 10 11 capture disabled rising edge falling edge both edges - pa3 rising edge pa3 falling edge pa3 both edges 00 pa2 00 01 10 11 capture disabled rising edge falling edge both edges - pa2 rising edge pa2 falling edge pa2 both edges table 20-15: capture condition selection capfunc(1:0) and capsel(1:0) can be modified only when the co unters are stopped otherwise data may be corrupted during one counter clock cycle. due to the synchronization mechanism of the shado w registers and depending on the frequency ratio between the capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective capture conditi on occurred. when the counters a and b are not cascaded and do not operate on the same clock, the interruptions on irqa and irqb which inform that the capture condition was met, may appear at different moments. in this case, the processor should read the shadow register associated to a counter only if the interruption related to this counter has been detected. an edge is detected on the capture signals only if th e minimal pulse widths of these signals in the low and high states are higher than a per iod of the counter clock source.
20-11 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 20.12 specifications parameter min typ max unit conditions 500 ns @ 1.2v pulse width in the low and high states for an external clock source, frequency division by 2 disabled 125 ns @ 2.4v 100 ns @ 1.2v pulse width in the low and high states for an external clock source, frequency division by 2 enabled 25 ns @ 2.4v pulse width of external capture signals 1 fckcnt s table 20-16: timing specifications for the counters
21-1 the voltage level detector ? 1.2 ? 24 mai 2000 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 21. the voltage level detector 21.1 f eatures ............................................................................................................................... 21-2 21.2 o verview ............................................................................................................................... 21-2 21.3 r egister map .........................................................................................................................21-2 21.4 i nterrupt map .......................................................................................................................21-2 21.5 vld operation ......................................................................................................................21-3
21-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 21.1 features ? can be switched off, on or simu ltaneously with cpu activities ? generates an interrupt if power supply is below a pre-determined level 21.2 overview the voltage level detector monitors the state of the system battery. it returns a logical high value (an interrupt) in the status register if the suppli ed voltage drops below the user defined level (vsb). 21.3 register map there are two registers in the vld, namely regvldctrl and regvldstat . table 21-2 shows the mapping of control bits and functionality of regvldctrl while table 21-3 describes that for regvldstat . register name regvldctrl regvldstat table 21-1: vld registers pos. regvldctrl rw reset function 7-4 -- r 0000 reserved 3 vldrange r w 0 nresetglobal vld detection voltage range for vldtune = ?011?: 0 : 1.3v 1 : 2.55v 2-0 vldtune[2:0] r w 000 nresetglobal vld tuning: 000 : +19 % 111 : -18 % table 21-2: regvldctrl pos. regvldstat rw reset function 7-3 -- r 00000 reserved 2 vldresult r 0 nresetglobal is 1 when battery voltage is below the detection voltage 1 vldvalid r 0 nresetglobal indicates when vldresult can be read 0 vlden r w 0 nresetglobal vld enable table 21-3: regvldstat 21.4 interrupt map interrupt source default mapping in the interrupt manager irqvld regirqmid(2) table 21-4: interrupt map
21-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 21.5 vld operation the vld is controlled by vldrange , vldtune and vlden . vldrange selects the voltage range to be detected, while vldtune is used to fine-tune this voltage level in 8 steps. vlden is used to enable (disable) the vld with a 1(0) value respective ly. disabled, the block will dissipate no power. symbol description min typ max unit comments trimming values: note 1 vldrange vldtune 1.53 0 000 1.44 0 001 1.36 0 010 1.29 0 011 1.22 0 100 1.16 0 101 1.11 0 110 1.06 0 111 3.06 1 000 2.88 1 001 2.72 1 010 2.57 1 011 2.44 1 100 2.33 1 101 2.22 1 110 vth threshold voltage 2.13 v 1 111 t eom duration of measurement 2.0 2.5 ms note 2 t pw minimum pulse width detected 875 1350 us note 2 table 21-5: voltage level detector operation note 1: absolute precision of the threshold voltage is 10%. note 2: this timing is respected in case the internal rc or crystal oscillators are selected. refer to the clock block documentation in case the external clock is used. to start the voltage level detection, the user sets bit vlden . the measurement is started. after 2ms, the bit vldvalid is set to indicate that the measurement resu lts are valid. from that time on, as long as the vld is enabled, a maskable interrupt request is s ent if the voltage level falls below the threshold. one can also poll the vld and monitor the ac tual measurement result by reading the vldresult bit of the regvldstat . this result is only valid as long as the vldvalid bit is ?1?.
21-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver figure 21-1 shows the timing of the vld. an in terrupt is generated on each rising edge of vldresult . figure 21-1: vld timing the threshold value should not be changed during the measurement. vbat vld_en vld_valid vld_result t eom pw pw vth
22-1 low power comparators ? 1.2 ? 06 aout 2003 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 22. low power comparators 22.1 f eatures ............................................................................................................................... 22-2 22.2 o verview ............................................................................................................................... 22-2 22.3 r egister map .........................................................................................................................22-3 22.4 i nterrupt map .......................................................................................................................22-4
22-2 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 22.1 features the cmpd peripheral implements four low power comparators. ? quiescent current consumption of 1.5 a ? very low switching current ? per channel configurable interrupt ? hysteresis ? 1 mhz operation 22.2 overview figure 22-1 gives an overview of this block: 4 4 4 3 regcmpdctrl(7:5) regcmpdstat(7:4) regcmpdctrl(4:0) 5 4 regcmpdstat(3:0) 4x irqonrisingch (edge selection) enirqch (channel enable) comparator output pb[7:4] enable comparators (analog) cmpd interrrupt figure 22-1: structure of cmpd
22-3 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver the cmpd peripheral is a 4-channel low power comparator. it is intended to compare analog input signals with an internally set threshold voltage. the comparator maintains low current consumption even if the input signal is very close to the thre shold. the comparison result of each channel can be used to generate an interrupt and/or is available for polling. the comparator can be enabled or disabled by programming the enable bit in the regcmpdctrl register. when disabled, the block consumes no current. the peripheral has a single interrupt output whic h is a combination of the four channels. the combination can be chosen by programming the regcmpdctrl register. the enirqch[3:0] bits select the channel that can activate the interrupt. the irqonrisingch[2:0] bits indicate if the interrupt is generated on detection of the rising or falling edge of the channel. the comparison results of the peripheral can be read in the regcmpdstat register. the bits cmpdout[3:0] are the value of the comparisons at the moment the register is read. the cmpdstat[3:0] indicates which channel generated an interrupt since the register was last read. comparator specifications: sym description min typ max unit comments t pulse required input pulse width 500 ns vbat 1.2v idd q quiescent current 0.8 1.5 a 1 idd stat maximal static current 1.5 a 2 v th threshold voltage 0.7 1.1 v 3 ? v th / ? t threshold temperature drift -0.9 mv/ c v hyst threshold hysteresis 13 mv table 22-1: comparator specifications comments: 1. the quiescent current is defined for a static input voltage <0.5v or >1.3v. the specified consumption is the sum for all 4 channels. 2. the maximal static current is defined for an y static input voltage between vdd and vss. the specified consumption is the sum for all 4 channels. 3. defined with respect to vss. how to start the cmpd: to avoid unwanted irqs one has first to configur e the rising / falling edge of the detection (bit irqonrisingch[2:0]) and to enable the comparator (b it enable). only after that may the user enable the channel interrupts with bit enirqch[3:0]. 22.3 register map there are two register s in the cmpd, namely regcmpdstat and regcmpdctrl . table 22-3 and table 22-4 show the mapping of the control bi ts and the functionalit y of these registers. register name regcmpdstat regcmpdctrl table 22-2: cmpd registers
22-4 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver pos. regcmpdstat rw reset function 7 cmpdstat[3] rc 0 nresetglobal 1: if the channel 3 generated an interrupt since last read of this register 6 cmpdstat[2] rc 0 nresetglobal 1: if the channel 2 generated an interrupt since last read of this register 5 cmpdstat[1] rc 0 nresetglobal 1: if the channel 1 generated an interrupt since last read of this register 4 cmpdstat[0] rc 0 nresetglobal 1: if the channel 0 generated an interrupt since last read of this register 3 cmpdout[3] r 0 nresetglobal channel 3 comparator output 2 cmpdout[2] r 0 nresetglobal channel 2 comparator output 1 cmpdout[1] r 0 nresetglobal channel 1 comparator output 0 cmpdout[0] r 0 nresetglobal channel 0 comparator output table 22-3: regcmpdstat pos. regcmpdctrl rw reset function 7 irqonrisingch[2] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channels 2 and 3. 0: an interrupt is generated on the falling edge of channels 2 and 3. 6 irqonrisingch[1] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channel 1. 0: an interrupt is generated on the falling edge of channel 1. 5 irqonrisingch[0] rw 0 nresetglobal 1: an interrupt is generated on the rising edge of channel 0. 0: an interrupt is generated on the falling edge of channel 0. 4 enirqch[3] rw 0 nresetglobal 1 enables interrupt on channel 3 3 enirqch[2] rw 0 nresetglobal 1 enables interrupt on channel 2 2 enirqch[1] rw 0 nresetglobal 1 enables interrupt on channel 1 1 enirqch[0] rw 0 nresetglobal 1 enables interrupt on channel 0 0 enable rw 0 nresetglobal enables the comparator table 22-4: regcmpdctrl 22.4 interrupt map interrupt source default mapping in the interrupt manager cmpd_irq regirqhigh[2] table 22-5: interrupt map
23-1 lc02 - 1.0 ? 05 november 2001 d0309-134 datasheet XE88LC02 sensing machine data acquisition mcu with zooming adc and lcd driver 23 physical dimensions 23.1 qfp type package the qfp package dimensions are given in figure 23-1 and table 23-1 figure 23-1. qfp type package package a mm b mm c mm d mm e mm f mm lqfp-80 14.0 14.0 1.4 0.10 0.32 0.65 lqfp-100 14.0 14.0 1.4 0.10 0.22 0.5 table 23-1. qfp package dimensions ? xemics 2003 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher fo r any consequence of its use. p ublication thereof does not con vey nor imply any license under patent or other industria l or intellectual property rights. xemics products are not designed, intended, authoriz ed or warranted to be suitable for use in life- support applications, devices or sy stems or other critical applications . inclusion of xemics products in such applications is understood to be undert aken solely at the customer?s own risk. should a customer purchase or use xemics products for any such unauthorized application, the customer shall indemnify and hold xemics and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and a ttorney fees which could arise.

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